實現於RISC架構之H.264視訊編碼複雜度控制

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姓名

黃振原(Jhen-Yuan Huang) 查詢紙本館藏

畢業系所

通訊工程學系

論文名稱

實現於RISC架構之H.264視訊編碼複雜度控制
(Complexity Control for H.264 Video Coding on RISC processors)

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摘要(中)

隨著行動多媒體的蓬勃發展，相關研究及應用引起越來越多的關注與討論。行動裝置輕薄短小、攜帶方便，同時卻被賦予能夠支援多種多媒體功能的期望，如：影像擷取與播放、即時視訊通訊、電影與電視之播放……等等。為了使行動裝置在有限電源供應下同時能夠支援如此高運算量、高頻寬之要求，電力知曉 (Power Aware) 的設計觀念被應用在電力最佳化。
電力知曉視訊編碼系統不僅是低功耗的設計，亦能針對無線視訊編碼系統，依據電池可供電剩餘時間調整編碼之複雜度動態調整功耗，以達到延長電池可供電時間之目的。
本研究提出一參數化的視訊編碼架構。除了可以完全調整功耗，同時引入以人類主觀視覺之視訊品質評估方式，建立一個功率-位元率-失真 (Power-Rate-Distortion) 之視訊編碼系統模型。該系統可以調整其複雜度控制參數以符合行動裝置所能提供之能量，同時將視訊品質提升至最高。
本研究在Intel Xscale處理器開發平台上實際探討，並針對平台撰寫SAD(sum of absolute difference)組合語言，以減少編碼時間。實驗結果顯示，此視訊編碼模型可減少系統高達75%之功耗。

摘要(英)

Mobile multimedia is a rising trend. Related research and application topics attract more and more attention. The expectation for a mobile device is light, thin, small, but powerful enough to support the increasing number of multimedia functions, such as photo capture and display, real-time video communications, and movies and TV display. To support these operations with high computing and high bandwidth requirements on a mobile device with limited energy, the power aware design concept is applied for achieving power optimization.
A power aware video coding system is not only a conventional low power design, but also a design that can adaptively adjust its encoding complexity based on the remaining battery supply to prolong the battery life.
We develop a parametric video encoding architecture, which is fully scalable in power consumption, and import a quality metric for subjective video quality measure. we establish a power-rate-distortion model of the video encoding system. The system is able to adjust its complexity control parameters based on the available energy supply of the mobile device while maximizing the picture quality.
A development platform based on the Intel’s Xscale microprocessor has been developed. SAD (sum of absolute difference) function is accelerated by assembly code to reduce encoding time. Experiments show that the system is able to save up to 75% power consumption in video coding based on this model.

關鍵字(中)

★ 複雜度控制
★ H.264視訊編碼
★ 嵌入式系統

關鍵字(英)

★ H.264 vdeo encoder
★ embedded system
★ complexity control

論文目次

摘要 i
ABSTRACT ii
一、緒論 1
1-1 研究背景 1
1-2 研究動機與目的 1
1-3 論文架構 2
二、視訊壓縮標準與RISC架構之最佳化程式 4
2-1 H.264視訊壓縮標準簡介 4
2-1-1 整體壓縮效能改進情形 5
2-1-2 H.264架構介紹 6
2-1-3 網路提取層 6
2-1-4 視訊編碼層 7
2-2 實現於RISC架構之最佳化程式 18
2-2-1 ARM組合語言與最佳化技巧 18
2-2-2 編寫對SAD函數的WMMX程式碼 19
2-2-3 實驗結果 22
三、H.264複雜度控制系統 25
3-1 相關研究 25
3-2 電力知曉概念 26
3-3 電力知曉視訊編碼設計 28
3-4 功率-位元率-失真架構 28
3-4-1 可調複雜度H.264編碼器 29
3-4-2 編碼造成之功耗 43
3-4-3 失真評判標準 (Quality Metric) 45
3-4-4 功率-位元率-失真模型 46
3-4-5 在功耗限制下位元率與失真運作方式 47
四、實驗結果分析與討論 49
4-1 視訊樣本與環境參數 49
4-2 複雜度級別之功耗分析 50
五、結論與未來研究建議 70
參考文獻 71

參考文獻

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指導教授

張寶基(Pao-Chi Chang)

審核日期

2008-7-8

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