博碩士論文 108523038 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:12 、訪客IP:3.15.174.76
姓名 林禹㨗(Yu-Chieh Lin)  查詢紙本館藏   畢業系所 通訊工程學系
論文名稱 以RFSoC平台實現多模式毫米波寬頻OFDM收發機與其應用
(Implementation of Multi-mode Wideband OFDM mmWave Transceiver and Application with RFSoC Platform)
相關論文
★ WiMAX基地台信號覆蓋實地量測與分析★ 被動元件阻抗量測原理及實務
★ 正交分頻多工接收機中數位降頻器之低通濾波器設計★ 適用於數位電視之里德所羅門編解碼硬體實作
★ 數位電視地面廣播系統之通道估測與等化器設計與實現★ 數位電視地面廣播之數位基頻收發機即時軟體設計與實現
★ 數位電視地面廣播系統通道解碼之腓特比解碼器實現★ 無線區域網路收發機之整合實現與測試
★ 以DSP處理器實現數位電視地面廣播系統發射機★ 數位電視內接收機同步系統之設計與實現
★ AIS實體層(GMSK/FM)與資料鏈結層軟體無線電技術實現★ 數位電視地面廣播系統內接收機之快速傅立葉轉換處理器研究與設計
★ 數位電視地面廣播之數位降頻器與再取樣器設計與實現★ 軟體無線電任意基頻訊號接收機系統設計及實現
★ 陣列天線互耦及接收機增益與相位對波束合成器性能影響及校正研究★ 適用於OFDM系統之可變長度快速傅立葉轉換處理器設計與實現
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 隨著無線通訊技術的進步,5G已經開始蓬勃發展,並期望能應用在物聯網與車用電子甚至是遠端手術等,對於資料的傳輸速度以及資料量的需求越來越高。因此我們希望能開發出符合此需求的收發機,並且完成實際的應用。為了實現高傳輸速度與高資料量的收發機模組,透過多路平行處理架構同時處理多筆資料,以硬體資源提高資料處理速度,最終利用FPGA實現實際的訊號收發。
在本論文中,我們設計收發機硬體架構並以Verilog硬體描述語言實現,收發機規格參考LTE DownLink架構下的OFDM調變系統,並搭配上DVB-T架構之通道編解碼規格進行修改與擴充。以上述規格開發出傳輸速度與資料量高的可靠收發機模組,並在RFSoC平台實現與使用號角天線及升降頻模組達成毫米波段之收發,最後展示其在中頻與毫米波段不同通道下的結果。
本論文另一重點是RFSoC與毫米波升降頻器開發板的使用,簡單講述如何利用PYNQ開發RFSoC並且實現RFSoC與電腦間的資料傳輸,還有RFSoC內各項基本矽智財的使用與其參數說明及設定,以及毫米波升降頻器開發板的使用與參數設定。
摘要(英) With the advancement of wireless communication technology, 5G has begun to flourish, and it is expected to be applied to the Internet of Things, automotive electronics and even remote surgery. The demand for transmission speed and data quantity is getting higher and higher. In order to achieve high transmission speed and high data quantity, we use parallel processing architecture to process multiple data at the same time. Increase data processing spend by hardware resources. Finally, complete the actual signal sending and receiving by FPGA.
Designed with Verilog hardware description language in the hardware. The transceiver module refers to the OFDM modulation system under the LTE DownLink architecture along with the channel decoding specification under the DVB-T architecture to modify and expand. Develop the reliable transceiver module with high transmission speed and large data quantity, and finally completed it on the RFSoC platform. Use up/down converter and horn antenna to achieve transmission in the millimeter wave band. Eventually show the result of the IF and millimeter wave bands.
Another focus of this thesis is the use of RFSoC and millimeter wave frequency converter development board. Briefly describe how to use PYNQ to develop RFSoC and achieve data transmission between RFSoC and computer. Descript the parameters and settings of basic silicon intellectual property of RFSoC and the settings of millimeter wave frequency converter development board.
關鍵字(中) ★ LTE
★ 正交分頻多工
★ 收發機
★ RFSoC
★ FPGA
★ 寬頻
★ PYNQ
★ 軟體定義無線電
★ 毫米波
關鍵字(英) ★ LTE
★ OFDM
★ Transceiver
★ RFSoC
★ FPGA
★ Wideband
★ PYNQ
★ Software-defined-radio
★ mmWave
論文目次 中文摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 viii
表目錄 xv
第一章 緒論 1
1-1 研究動機與背景 1
1-2 章節簡介 2
第二章 寬頻OFDM收發機系統簡介 3
2-1 Tx Buffer Engine 9
2-2 封包產生器 10
2-3 星座圖映射(QAM Mapping) 12
2-4 參考訊號(Pilot) 12
2-5 快速傅立葉轉換(Fast Fourier Transform) 14
2-6 循環字首(Cyclic Prefix) 15
2-7 符元時序同步(Symbol Timing Synchronization) 16
2-7-1 符元時序偏移討論 16
2-7-2 符元時序同步原理 17
2-8 自動增益控制(Automatic Gain Control) 18
2-9 載波頻率同步(Carrier Frequency Synchronization) 20
2-9-1 載波頻率誤差之影響 20
2-9-2 載波頻率同步原理 22
2-10 通道估測(Channel Estimation) 23
2-10-1直接決策通道估測 23
2-10-2取樣後維持通道估測 25
2-11 同步位元組偵測器 25
2-12 解擾亂器 26
2-13 空封包偵測器 27
2-14 Rx Buffer Engine 28
第三章 寬頻OFDM發射機硬體實現 29
3-1 Tx Buffer Engine 30
3-2 封包產生器 32
3-3 星座圖映射器 34
3-4 參考訊號(Pilot) 35
3-5 訊框架構器 35
3-6 子載波映射器 37
3-7 快速反傅立葉轉換器 38
3-6-1 IFFT與FFT切換 41
3-6-2 碟型運算器 41
3-6-3 座標軸數位旋轉計算器 43
3-6-4 多路位元反轉排序 45
3-8 循環字首置入器 46
第四章 寬頻OFDM接收機硬體實現 48
4-1 自動增益控制(Automatic Gain Control) 49
4-2 符元時序同步器(Symbol Timing Synchronizer) 50
4-2-1 延遲相關器 50
4-2-2 峰值檢測器 52
4-2-3 符元同步器 54
4-3 載波頻率同步器(Carrier Frequency Synchronizer) 55
4-4 解子載波映射器 56
4-5 解訊框架構器 58
4-6 通道估測與等化 60
4-6-1 參考訊號通道響應 61
4-6-3 通道等化 63
4-7 同步位元組偵測器 65
4-8 解擾亂器與空封包偵測器 67
4-9 Rx Buffer Engine 68
第五章 RFSoC平台之實現 70
5-1 RFSoC(射頻系統單晶片) 70
5-2 RFSoC平台 71
5-2-1 RFSoC DAC/ADC 72
5-2-2 RFSoC Clock 74
5-2-3 RFSoC Nyquist Zone Operation 75
5-2-4 RFSoC DAC/ADC資料之擺放 76
5-2-5 RFSoC DAC/ADC 操作介面 80
5-2-6 RFSoC DMA操作介面 82
5-2-7 RFSoC平台使用流程 84
5-3 毫米波段升降頻開發板 88
5-3-1 毫米波段之頻率合成器 88
5-3-2 毫米波段之升頻器 91
5-3-3 毫米波段之降頻器 94
第六章 寬頻OFDM收發機應用 97
6-1 數據流組成方式 97
6-2 文字檔傳輸 98
6-3 圖片傳輸 99
第七章 RFSoC平台模擬與硬體實現結果 101
7-1 中頻波段之實驗環境與結果 101
7-1-1 發射機訊號之頻譜圖 102
7-1-2 RFSoC發射功率與接收功率校正結果 105
7-1-3 OFDM收發機之實驗結果 106
7-1-4 中頻波段之系統定點數與浮點數錯誤率比較 112
7-2 毫米波段之實驗環境與結果 113
7-2-1 發射機訊號毫米波段頻譜圖 115
7-2-2 2K Mode接收機毫米波段訊號 118
7-2-3 4K Mode接收機毫米波段訊號 121
7-2-4 毫米波段系統頻偏測試 123
7-3 系統使用資源 124
第八章 結論 127
參考文獻 128
參考文獻 [1] Chang-Yueh. Liu, “Design and Implementation of Wideband OFDM Transceiver with SDR Platform” National Central University, Master’s thesis, Dec. 2019.
[2] Tzu-Chun. Liu, “Implementation of High Throughput Codec for Wideband OFDM Tranceiver with SDR Platform” National Central University, Master’s thesis, Dec. 2019.
[3] Guan-Ciou Huang “Implementation of Wideband OFDM mmWave Transceiver with RFSoC Platform” National Central University Master’s thesis, Oct, 2020.
[4] C.H. Kuo, “Design and Implementation of Viterbi Decoder for Multi-Rate Convolutional Code in DVB-T System” National Central University, Master’s thesis, Jul. 2010.
[5] Yih-Min Chen, Hsin-Yin Wu, and Mong-Yo Lu. “Decision-directed polynomial model-based channel estimation for ofdm systems with scattered-pilots,” in ITS Telecommunications (ITST), 2012 12th International Conference on, pages 748-752. Nov, 2012.
[6] Jae-Sun Han, Tae-Jin Kim, Chanho Lee, “High performance Viterbi decoder using modified register exchange methods,” in 2004 IEEE International Symposium on Circuits and Systems, Vol.3, Page(s):III – 553-6, May 2004
[7] D. A. F. Ei-Dib and M. I. Elmasry, “Low-power register-exchange Viterbi decoder for high-speed wireless communications,” IEEE ISCAS, Vol. 5, pp. V737~740, May. 2002.
[8] Feygin, G.; Gulak, P, “Architectural tradeoffs for survivor sequence memory management in Viterbi decoder,” Communications, IEEE Trans. On Communications, Vol 41, Issue 3, Page(s):425~429, March 1993
[9] T. K. Truong, M. –T. Shih, I. S. Reed, and E. H. Satorius, “ A VLSI design for a trace-back Viterbi decoder,” IEEE Trans. on Communications, Vol. 40, No.3, pp.616~624, Mar. 1992.
[10] Ivan M. Onyszchuk, “Truncational Length for Viterbi Decoding,” IEEE Trans. On Communication, Vol.COM-39, pp.1023~1026, July 1991.
[11] C. B. Shung, P. H. Siegel, G. Ungerboeck, and H. K. Thapar, “VLSI architectures for metric normalization in the Viterbi algorithm,” IEEE ICC, Vol. 4, pp.1723-1728, Apr.1990.
[12] F. Weng, C. Yin, and T. Luo,” Channel estimation for the downlink of 3gpp lte systems,” in Network Infrastructure and Digital Content, 2010 2nd IEEE International Conference on, pages. 1042-1046, Spet. 2010.
[13] Q. Wang, C. Mehlfuhrer, and M. Rupp, “Carrier frequency synchronization in the downlink of 3gpp lte,” in 21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, pages. 939–944, 2010.
[14] A. Peled and A. Ruiz, “Frequency domain data transmission using reduced computational complexity algorithms,” in Acoustics, Speech, and Signal Pro- cessing, IEEE International Conference on ICASSP’80, vol. 5, pages. 964–967, IEEE, 1980.
[15] J. E. Volder, “The cordic trigonometric computing technique,” IRE Transac- tions on Electronic Computers, no. 3, pages. 330–334, 1959.
[16] M.-X. Chang and Y. T. Su, “Model-based channel estimation for OFDM signals in Rayleigh fading,” IEEE Transactions on Communications, vol. 50, no. 4, pp. 540-544, 2002.
[17] H. G. Myung, J. Lim, and D. J. Goodman, “Peak-to-average power ratio of single carrier fdma signals with pulse shaping,” in Personal, Indoor and MobileRadio Communications, 2006 IEEE 17th International Symposium on, pp. 1-5, 2006.
[18] A. Sohl, T. Frank, and A. Klein, “Channel estimation for dft precoded ofdma with blockwise and interleaved subcarrier allocation,”in Proc. International OFDM Workshop 2006
[19] X. Wang and K. R. Liu, “Channel estimation for multicarrier modulation sys-tems using a time-frequency polynomial model," IEEE transactions on commu-nications, vol. 50, no. 7, pp. 1045-1048, 2002.
[20] Xilinx(2018, Decdmber 5). Zynq UltraAcale+ RFSoC RF Data Converter Evaluation Tool(ZCU111) User Guide. Retrieved from
https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-eval-bd.pdf
[21] Xilinx(2018, April 17). Zynq UltraScale+ RFSoC RF Data Converter 2.0 LogiCORE IP Product Guide. Retrieved from
https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_0/pg269-rf-data-converter.pdf
[22] Arm Developer. AMBA 4 AXI4-Stream Protocol Specification. Retrieved from
https://developer.arm.com/documentation/ihi0051/a?lang=en
[23] Xilinx. PYNQ:PYTHON PRODUCTIVITY. Rertieved from
http://www.pynq.io/
[24] ANALOG DEVICES. ADF4372: Microwave Wideband Synthesizer with Integrated VCO. Retrieved from
https://www.analog.com/en/products/adf4372.html
[25] ANALOG DEVICES. ADNV1013: 24GHz to 44GHz, Wideband, Microwave Upconverter. Retrieved from
https://www.analog.com/en/products/admv1013.html
[26] ANALOG DEVICES. ADMV1014: 24GHz to 44GHz, Widebnd, Microwave Downconverter. Retrieved from
https://www.analog.com/en/products/admv1014.html
[27] A-INFO. Standard Gain Horn Antenna: LB-28-20-C-XX. Retrieved from
http://www.ainfoinc.com.cn/en/pro_pdf/new_products/antenna/Standard%20Gain%20Horn%20Antenna/tr_LB-28-20.pdf
[28] K. Sobaihi, A. Hammoudeh, D. Scammell, “Automatic Gain Control on FPGA for Software-Defined Radios,” in London, UK, 2012 Wireless Telecommunications Symposium, IEEE Aug. 2012.
指導教授 陳逸民(Yih-Min Chen) 審核日期 2021-8-20
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明