| 摘要(英) |
Second generation digital video satellite broadcasting(DVB-S2) is a new generation of digital satellite broadcasting standard specified for enhancing transmission capacity of the DVB-S. The main improvement of DVB-S2 relies on the new channel coding scheme which use LDPC(low-dansity-parity-check) code and BCH(Bose–Chaudhuri–Hocquenghem) code. And in the DVB-S2 specification, different code lengths and code rates are also provided, which can correspond to various needs.
The research topic of this thesis is on the hardware architecture design and realization of the decoder for the complete DVB-S2 LDPC specification with ZCU102 FPGA evaluation board. Since all the parity matrices specified in the multi-rate DVB-S2 LDPC codes can be transformed in QC(quasi-cyclic)-LDPC codes particular reordering of data and parity-check, we uses a partial parallel and programmable hardware architecture, which is specially designed for QC-LDPC codes and based on a scanning scheme, as the hardware architecture of the decoder. The hardware architrcture includes parallel scanning parameters, control module, block circshift module, and soft input soft output decoding calculation module and decoding information update module. Among them, the related parameters of multi-bit rate and code length are stored in memory and the special data structure is completed in a look-up table mode. The SISO decoding algorithm uses the Min-Sum algorithm as the base to reduce the hardware complexity. The decoder implemented in this thesis can be achieved by external input parameters and control signals to change the corresponding DVB-S2 specification LDPC code rate and code length of the next set of incoming data during operation. |
| 參考文獻 |
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[8] Y.-M. Chen and P.-H. Wen, “Design and fpga implementation of a configurable multi-rate QC-LDPC decoder with raster scanning architecture”, APWCS-2010.
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[10] 黃偉倫 陳逸民. (2015). DVB-S2 LDPC解碼器之FPGA設計與實現. |
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