| 姓名 |
康栚洲(JEN-JOU KANG)
查詢紙本館藏 |
畢業系所 |
通訊工程學系 |
| 論文名稱 |
以 RFSoC平台設計與實現DVB-S2訊號數位中繼器
(Design and Implementation of Digital Repeater for DVB-S2 Signal with RFSoC Platform)
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| 相關論文 | |
| 檔案 |
 [Endnote RIS 格式]
[Bibtex 格式]
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| 摘要(中) |
近期以低軌道通訊衛星群提供全球隨時隨地高資料率行動上網技術成為熱門的研究課題與技術發展方向，於是採用第二代數位廣播 (DVB-S2)，除了QPSK，更提供 8PSK、16APSK、32APSK等多種調變方式，更能適應線性特性相對不好的衛星傳輸通道。
本論文在RFSoC平台實現DVB-S2之收發機。在發射機中，包含了BCH code、LDPC code和調變器，接收機則包含時間同步、頻率同步、相位同步，時間同步採用內插器，以消除時序偏移並進行同步取樣，頻率同步則是以固定星座圖去計算及修正頻率偏移，相位同步則是以已知的Start Of Frame (SOF) 來修正相位，並增加自動偵測調變機制 (MODCOD-Detector) ，以便後續解碼器所用，將其整合實現DVB-S2收發機。並實現數位中繼器 (Digital Repeater) 的應用，可應用在衛星酬載中用以重新產生任意調變及碼率之訊號，獲取之訊號放大以及重新產生，使得訊號恢復強度以及質量，降低傳輸時訊號衰減以及失真的影響在高速傳收上增進訊號之品質。 |
| 摘要(英) |
Recently, providing high data rate mobile internet access anytime and anywhere through low Earth orbit communication satellite networks has become a popular research topic and technical development direction. The second-generation digital broadcasting (DVB-S2) is adopted, which provides multiple modulation methods such as QPSK, 8PSK, 16APSK, and 32APSK to adapt to satellite transmission channels with relatively poor linear characteristics.
This paper implements a DVB-S2 transceiver on the RFSoC platform. The transmitter includes BCH code, LDPC code, and modulator, while the receiver includes time synchronization, frequency synchronization, and phase synchronization. Time synchronization uses an interpolator to eliminate timing offset and perform synchronous sampling. Frequency synchronization uses a fixed constellation diagram to calculate and correct frequency offset. Phase synchronization corrects the phase using the known Start Of Frame (SOF) and adds an automatic modulation code (MODCOD-Detector) detection mechanism for subsequent decoder use, integrating it into the DVB-S2 transceiver implementation. The paper also implements the application of a Digital Repeater, which can be used in satellite payloads to regenerate signals of any modulation and code rate. The obtained signal is amplified and regenerated, restoring signal strength and quality, improving signal quality for high-speed transmission and reception, and reducing the effects of signal attenuation and distortion during transmission. |
| 關鍵字(中) |
★ 第二代數位廣播
★ 數位中繼器
★ 收發機
★ RFSoC
★ 軟體定義無線電
★ FPGA |
關鍵字(英) |
★ Digital Video Broadcasting-Satellite-Second Generation
★ Digital Repeater
★ Transceiver
★ RFSoC
★ Software-defined-radio
★ FPGA |
| 論文目次 |
中文摘要 i
Abstract ii
目錄 iii
圖目錄 iv
表目錄 v
第一章 緒論 1
1.1 研究動機與背景 1
1.2 章節簡介 2
第二章 DVB-S2規格簡介 3
2.1 DVB-S2流程架構 3
2.2 Frame架構 4
2.2.1 FEC Frame 4
2.2.2 PL Frame 6
2.2.3 PL Header 7
2.3 Frame內部建構運作 8
2.3.1 Bit Interleaver 8
2.3.2 PL Scrambling 10
2.4 Bit Mapping 11
2.4.1 QPSK 11
2.4.2 8PSK 11
2.4.3 16APSK 12
2.4.4 32APSK 13
第三章 DVB-S2收發機系統 14
3.1 發射端編碼處理 14
3.1.1 BB Scrambling 14
3.1.2 BCH Encoder 15
3.1.3 LDPC Encoder 16
3.1.4 Bit Interleaver 16
3.2 Constellation Mapping 18
3.3 PLHeader 18
3.4 適應編碼調製機制 20
3.4.1 DVB-S2發射端架構與參數 20
3.4.2適應編碼調製機制 21
3.5 升降取插值濾波器(Up-Down sample Interpolation Filter) 23
3.6 接收端流程架構 24
3.6.1 接收端架構 24
3.6.2 接收端訊號模型 24
3.7 再取樣(Resampling) 27
3.7.1 費洛內插器(Farrow Interpolator) 27
3.7.2 Cubic Lagrange Interpolator 29
3.8 匹配濾波器(Matched Filter) 30
3.9 符碼同步(Symbol Synchronization) 31
3.9.1 符碼同步原理架構 33
3.10 載波同步(Carrier Synchronization) 35
3.10.1 DVB-S2訊號規格Hard-Decision 36
3.10.2 載波同步原理架構 40
3.11 Frame同步 41
3.11.1 相關器(correlator) 41
3.11.2 Descrambling 44
3.12 自動偵測調變 45
3.13 自動增益控制(Automatic Gain Control) 46
第四章 硬體架構實現 48
4.1 Squar Root Raise Cosine 48
4.1.1 Poly phase 48
4.1.2 SRRC模組 49
4.1.3 SRRC架構 50
4.1.4 升降取插值濾波器 51
4.1.5 升降取插值濾波器架構 53
4.2 符碼同步模組 54
4.2.1 Farrow Interpolator 55
4.2.2 Timing Error Detector 59
4.3 載波同步模組 60
4.3.1 Decision-Directed Phase-Error Estimator 61
4.3.2 Loop filter(carrier synchronization) 62
4.4 Frame同步與相位同步模組 62
4.4.1 相關器(Correlator) 63
4.4.2 自動偵測調變(MODCOD Detector 64
4.4.3 量化處理訊號bits數 64
4.4.4 MODCOD 相關器乘法簡化處理 66
4.5 自動增益控制(Automatic Gain Control) 68
第五章 RFSoC平台之實現 70
5.1 RFSoC(射頻系統單晶片) 70
5.2 RFSoC平台 71
5.2.1 RFSoC DAC/ADC 72
5.2.2 RFSoC Clock 75
5.3 DVB-S2 Digital Repeater 77
5.3.1 Repeater 執行流程圖 78
5.3.2 Repeater Buffer Engine 79
5.3.3 Repeater取樣率偏差之影響 81
5.3.4 Repeater個別模組之延遲 83
5.4 實驗結果 84
5.4.1 系統使用資源 85
5.4.2 收發機硬體實現結果 90
5.4.3 Repeater硬體實現結果 92
第六章 結論 95
參考文獻 96
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| 參考文獻 |
[1] Y.-M. Chen, “A simple carrier synchronization for dvb-s2 signals using polar decision-directed phase error estimator,”2014.
[2] Y.-M. Chen, “On the design of farrow interpolator for ofdm receivers with asynchronous if sampling,” in Communications and Networking in China, 2009. ChinaCOM 2009. Fourth International Conference on, pp. 1-5, IEEE, 2009.
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[9] K. Sobaihi, A. Hammoudeh, D. Scammell, “Automatic Gain Control on FPGA for Software-Defined Radios,” in London, UK, 2012 Wireless Telecommunications Symposium, IEEE Aug. 2012.
[10] Guan-Ciou Huang “Implementation of Wideband OFDM mmWave Transceiver with RFSoC Platform” National Central University Master’s thesis, Oct, 2020.
[11] P.-H. Chen, “Design and Implementation of DVB-S2 Transceiver with ACM function on SDR”,2022.
[12] Xilinx(2018, Decdmber 5). Zynq UltraAcale+ RFSoC RF Data Converter Evaluation Tool(ZCU111) User Guide. Retrieved from
https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-eval-bd.pdf
[13] Xilinx(2018, April 17). Zynq UltraScale+ RFSoC RF Data Converter 2.0 LogiCORE IP Product Guide. Retrieved from
https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_0/pg269-rf-data-converter.pdf
[14] Arm Developer. AMBA 4 AXI4-Stream Protocol Specification. Retrieved from
https://developer.arm.com/documentation/ihi0051/a?lang=en
[15] Xilinx. PYNQ:PYTHON PRODUCTIVITY. Rertieved from
http://www.pynq.io/
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| 指導教授 |
陳逸民(YI-MIN CHEN)
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審核日期 |
2023-4-20 |
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