DSpace community: 電機工程研究所

用於低秩適應微調之高效能記憶體存取與混合精度加速器架構設計;Memory-Access Efficient and Mixed-Precision Accelerator Architecture Design for LoRA Fine-Tuning

title: 用於低秩適應微調之高效能記憶體存取與混合精度加速器架構設計;Memory-Access Efficient and Mixed-Precision Accelerator Architecture Design for LoRA Fine-Tuning abstract: 大型語言模型在邊緣運算裝置上進行微調的挑戰包含外部記憶體資料搬移、低秩矩陣的不規則形狀，以及多精度訓練運算的硬體成本。本論文提出一套由 RISC-V 自訂指令控制、運用於低秩適配（Low-Rank Adaptation， LoRA）微調的混合精度加速器。首先將 LoRA 前向傳遞、反向傳遞與 AdamW 權重更新拆解為張量運算與個別元素運算，再透過矩陣分割、資料保留及晶片內部分和累加等技術降低中間資料搬移的能耗。混合精度核心透過共享的部分乘積產生器、多功能乘加單元（multi-function multiply-accumulate， MFMAC）與管線化區塊浮點數路徑來支援整數乘整數、浮點數乘整數及浮點數乘浮點數等運算。共享 MFMAC 核心相較於各模式獨立運作的乘法器可減少 24.8% 的面積。針對 LoRA 梯度的瘦高與寬扁矩陣，能耗模型在指定工作負載、緩衝容量與係數下選得 6.95 mJ 的動態分割排程，較其他三種傳統固定分割處理資料流降低 16.1% 至 59.1% 的能耗。系統架構整合全域緩衝區、四個張量單元、向量單元及自訂指令控制，以執行 LoRA 矩陣運算與 AdamW 更新。位元精確驗證中，張量單元的輸出與向量單元的輸出皆與軟體黃金模型逐位元一致。於固定模型、資料與單次訓練設定下，位元精確模型與 PyTorch LoRA 對照驗證，在 BoolQ 的正確率分別為 80.5810% 與 80.6422%，在 WinoGrande XL 分別為 73.88% 與 73.80%，XSum 的 ROUGE-L 則皆為 0.2919，未觀察到明顯的任務品質下降。硬體張量單元排程的週期利用率為 99.14% 至 100%；28 nm 前佈局合成與功耗估計顯示，設計在 400 MHz 下的面積為 3.1082 mm²，理論峰值吞吐量為 0.8192 TFLOPS，低秩梯度鏈與梯度回傳鏈的能源效率為 1.52 與 1.34 TFLOPS/W。上述結果顯示，所提出方法經位元精確驗證，具備以 LoRA 硬體加速器在邊緣運算裝置進行微調的可行性。關鍵詞：低秩適配、混合精度、張量加速器、能耗感知資料流、RISC-V 自訂指令、位元精確驗證;Low-rank adaptation (LoRA) of large language models on edge devices is constrained by external memory access， the irregular shapes of low-rank matrices， and the implementation cost of mixed-precision training. This thesis presents a mixed-precision accelerator controlled by RISC-V custom instructions for LoRA fine-tuning. The LoRA backward pass and AdamW update are decomposed into tensor and element-wise operations， while design strategies for matrix tiling， data retention， and on-chip partial-sum accumulation are proposed to reduce energy consumption. The shared multi-function multiply-accumulate (MFMAC) core supports integer-by-integer， floating-point (FP)-by-integer， and FP-by-FP operations， and achieves 24.8% less area than separately inferred multipliers. For the tall-and-skinny and wide-and-short matrices in LoRA gradients， the dynamic tiling schedule reduces energy consumption by 16.1%–59.1% compared with the three conventional fixed-tiling schemes. The system integrates a global buffer， four tensor units， a vector unit， and custom-instruction control to execute LoRA matrix operations and AdamW updates. All tensor-unit and vector-unit outputs match the software golden model bit for bit. The bit-true model differs from the PyTorch LoRA model by less than 1% on BoolQ and WinoGrande XL， and both obtain a ROUGE-L score of 0.2919 on XSum. The tensor units reach 99.14% to 100% cycle utilization for LoRA back propagation. Pre-layout synthesis and power estimation in a 28-nm process report an area of 3.1082 mm² at 400 MHz， a theoretical peak throughput of 0.8192 TFLOPS， and energy efficiencies of 1.52 and 1.34 TFLOPS/W for the LoRA parameter-gradient and gradient propagation workloads， respectively. These results show the feasibility of fine-tuning on edge devices.

碳膜與碳化鈦插入層改善AlGaN/GaN HEMT歐姆接觸特性之研究;Investigation of Improved Ohmic Contact Characteristics in AlGaN/GaN HEMTs Using Carbon and Titanium Carbide Interlayers

title: 碳膜與碳化鈦插入層改善AlGaN/GaN HEMT歐姆接觸特性之研究;Investigation of Improved Ohmic Contact Characteristics in AlGaN/GaN HEMTs Using Carbon and Titanium Carbide Interlayers abstract: 傳統氮化鋁鎵/氮化鎵高電子遷移率電晶體(AlGaN/GaN HEMT)之歐姆接觸多採用 Ti/Al/Ni/Au金屬堆疊，並經高溫快速熱退火形成低阻接觸。本研究於歐姆金屬與 AlGaN/GaN異質結構之間導入不同厚度之碳(C)與碳化鈦(TiC)插入層，並進一步結合孔洞式凹槽蝕刻結構，以探討其對歐姆接觸特性及元件電性的影響。首先，比較傳統型歐姆接觸結構、2 nm與5 nm碳插入層，以及1.5 nm與3 nm碳化鈦插入層之歐姆接觸特性。傳輸線模型(TLM)量測結果顯示，導入2 nm碳插入層可獲得最佳歐姆接觸特性，其接觸電阻與特徵接觸電阻率分別降低至Rc = 0.119 Ω·mm 與 ρc = 2.28 × 10-7 Ω·cm2，顯著優於傳統型歐姆接觸結構。元件直流特性分析亦顯示，2 nm碳插入層元件具有較低導通電阻、較低關閉漏電流及較高開關電流比。崩潰電壓量測結果顯示，導入碳或碳化鈦插入層後元件之耐壓特性未出現明顯劣化。於動態特性分析中，3 nm碳化鈦插入層元件於Gate-lag與Drain-lag條件下展現較低之電流崩塌率及較小之動態/靜態導通電阻比值，而2 nm碳插入層元件之動態特性亦優於傳統型歐姆接觸元件。此外，長時間熱儲存測試結果顯示，2 nm碳插入層元件具有較佳之熱穩定性。值得注意的是，雖然直接導入碳化鈦插入層亦可改善歐姆接觸特性，但其接觸電阻仍高於2 nm碳插入層元件，顯示碳插入層於退火過程中所誘發之界面反應及TiC界面相形成，對歐姆接觸改善具有更顯著之貢獻。為探討歐姆接觸改善機制，本研究進一步利用FIB與TEM進行材料分析。結果顯示，2 nm碳插入層可調控歐姆金屬與 AlGaN/GaN異質結構之間界面反應，促進TiC與TiN混合反應層形成，改變界面結構並降低有效蕭特基能障，進而改善歐姆接觸特性；3 nm碳化鈦插入層則促進TiN與TiCxN1-x混合反應層形成，顯示不同插入層在高溫快速熱退火後會有不同界面反應相組成，也導致不同的歐姆接觸特性。本研究亦探討孔洞式凹槽蝕刻結構搭配碳或碳化鈦插入層之影響。結果顯示，不同孔洞尺寸會影響歐姆接觸與元件電性，其中3 µm孔洞尺寸搭配2 nm碳插入層具有最佳表現。然而，相較於未導入凹槽蝕刻之2 nm碳插入層元件，孔洞式凹槽蝕刻結構並未進一步降低歐姆接觸電阻，顯示其改善效果有限。最後，透過熱離子場發射(TFE)與場發射(FE)模型擬合溫度相依特徵接觸電阻率，結果顯示導入2 nm碳插入層後可有效降低界面等效能障高度，兩者綜合顯示碳層誘發之界面反應可能與載子穿隧傳輸改善及接觸電阻降低有關。整體而言，本研究結果顯示，碳插入層可有效降低AlGaN/GaN HEMT之歐姆接觸電阻並改善元件導通特性；相較之下，孔洞式凹槽蝕刻結構雖可維持良好的元件電性，但並未進一步降低歐姆接觸電阻，其改善效果有限。;Conventional ohmic contacts for AlGaN/GaN HEMTs are commonly formed using a Ti/Al/Ni/Au metal stack followed by high-temperature annealing. In this study， carbon (C) and titanium carbide (TiC) insertion layers with various thicknesses were introduced between the ohmic metal stack and the AlGaN/GaN heterostructure. In addition， hole-type recessed structures were incorporated to investigate their effects on ohmic contact characteristics and device electrical performance. First， the ohmic contact characteristics of conventional contacts， 2 nm and 5 nm C insertion layers， and 1.5 nm and 3 nm TiC insertion layers were compared. TLM measurements showed that the 2 nm C insertion layer exhibited the best ohmic contact performance， with the contact resistance and specific contact resistivity reduced to Rc = 0.119 Ω·mm and ρc = 2.28 × 10-7 Ω·cm2， respectively， which were significantly lower than those of the conventional ohmic contact structure. DC characteristics also demonstrated that the device with the 2 nm C insertion layer exhibited a lower on-resistance， lower off-state leakage current， and higher on/off current ratio. Breakdown voltage measurements indicated that the introduction of C or TiC insertion layers did not cause significant degradation in the breakdown characteristics. Under dynamic operating conditions， the device with the 3 nm TiC insertion layer exhibited lower current collapse and smaller dynamic-to-static on-resistance ratios under both gate-lag and drain-lag conditions， while the dynamic performance of the device with the 2 nm C insertion layer was also superior to that of the conventional ohmic contact device. In addition， long-term thermal storage measurements showed that the device with the 2 nm C insertion layer exhibited better thermal stability. Notably， although direct insertion of a TiC layer also improved the ohmic contact characteristics， its contact resistance remained higher than that of the device with the 2 nm C insertion layer. This result suggests that the interfacial reactions induced by the C insertion layer during annealing and the resulting formation of an interfacial TiC phase make a more significant contribution to the improvement of ohmic contact characteristics. To investigate the mechanism underlying the improvement in Ohmic contact characteristics， FIB and TEM analyses were further performed. The results show that the 2 nm carbon insertion layer can modulate the interfacial reactions between the Ohmic metal stack and the AlGaN/GaN heterostructure， promoting the formation of a mixed TiC/TiN reaction layer. This modification of the interfacial structure reduces the effective Schottky barrier height， thereby improving the Ohmic contact characteristics. In contrast， the 3 nm TiC insertion layer promotes the formation of a mixed TiN/TiCxN1-x reaction layer. These results indicate that different insertion layers lead to distinct interfacial reaction phases after high-temperature RTA， resulting in different Ohmic contact characteristics. The effects of combining hole-type recessed structures with C or TiC insertion layers were also investigated. The results showed that different hole dimensions affected both the ohmic contact characteristics and device electrical performance， with the combination of 3 µm holes and a 2 nm C insertion layer exhibiting the best overall performance among the recessed structures. However， compared with the non-recessed device using the 2 nm C insertion layer， the hole-type recessed structure did not further reduce the ohmic contact resistance， indicating that its improvement in contact characteristics was limited. Finally， the temperature-dependent specific contact resistivity was analyzed using thermionic-field-emission (TFE) and field-emission (FE) models. The fitting results showed that the introduction of the 2 nm C insertion layer effectively reduced the effective interfacial barrier height. Combined with the material analysis results， these findings suggest that the interfacial reactions induced by the C insertion layer are associated with enhanced carrier tunneling transport and reduced contact resistance. Overall， the results demonstrate that the C insertion layer can effectively reduce the ohmic contact resistance of AlGaN/GaN HEMTs and improve their conduction characteristics. In contrast， although the hole-type recessed structure maintained favorable device electrical performance， it did not further reduce the ohmic contact resistance， and its improvement in ohmic contact characteristics was therefore limited.

應用於衛星通訊與感測之 Ku/U/W 頻段低雜訊放大器;Ku-， U-， and W-Band Low-Noise Amplifiers for Satellite Communications and Sensing

title: 應用於衛星通訊與感測之 Ku/U/W 頻段低雜訊放大器;Ku-， U-， and W-Band Low-Noise Amplifiers for Satellite Communications and Sensing abstract: 本論文為使用 WIN 120-nm GaN HEMT 製程，設計應用於衛星通訊與感測之 Ku 頻段低雜訊放大器，以及使用 WIN 100-nm GaAs pHEMT 製程來實現的 U 和 W 頻段低雜訊放大器。現今研究發展趨勢向微波與毫米波頻段遷移，並介紹 Ku、U、W 頻段。接著說明低雜訊放大器的重要性與設計上的挑戰。第一個電路使用 WIN 120-nm GaN HEMT NP12-01 製程，設計應用於 Ku 頻段之低雜訊放大器。採用了源極退化(source degeneration)架構。在 15 GHz 的頻率下，實現 7.6 dB 的增益，以及 3.1 dB 的雜訊指數。小訊號模擬與量測結果大致相符，雜訊指數則有後續改善的空間。第二個電路使用 WIN 100-nm GaAs pHEMT PP10-20 製程，設計應用於 U 頻段之低雜訊放大器。採用了共源共閘(cascode)架構。經由先前電路偵錯，修正電晶體模型，再進行電路設計。在 48 GHz 的頻率下，實現 19.3 dB 的增益，以及 2.4 dB 的雜訊指數。增益、雜訊指數較佳但反射損耗仍需要優化改善。第三個電路使用 WIN 100-nm GaAs pHEMT PP10-20 製程，設計應用於 W 頻段之低雜訊放大器。採用了共源共閘(cascode)架構。經由先前電路偵錯，修正電晶體模型，再進行電路設計。在 94 GHz 的頻率下，實現 13.7 dB 的增益，以及 3.9 dB 的雜訊指數。增益、雜訊指數較佳，但線性度不足的問題需要解決。;This thesis presents the design of a Ku-band low-noise amplifier for satellite communication and sensing using the WIN 120-nm GaN HEMT process， and U-band and W-band low-noise amplifiers implemented using the WIN 100-nm GaAs pHEMT process. Current research trends are shifting towards microwave and millimeter-wave frequency bands， and the Ku-， U-， and W-band are introduced. The importance of low-noise amplifiers and their design challenges are then explained. The first circuit， designed using a WIN 120-nm GaN HEMT NP12-01 process， is a low-noise amplifier applied to the Ku-band. It employs a source degradation architecture. At 15 GHz， it achieves a gain of 7.6 dB and a noise figure of 3.1 dB. Small-signal simulation and measurement results are largely in agreement， but there is room for further improvement in the noise figure. The second circuit， designed using a WIN 100-nm GaAs pHEMT PP10-20 process， is a low-noise amplifier applied to the U-band. It employs a cascode architecture. Following debugging of the previous circuit and correction of the transistor model， the circuit design was then carried out. At 48 GHz， it achieves a gain of 19.3 dB and a noise figure of 2.4 dB. While the gain and noise figure are good， the reflection loss still needs optimization and improvement. The third circuit， designed using a WIN 100-nm GaAs pHEMT PP10-20 process， is a low-noise amplifier applied to the W-band. It employs a cascode architecture. Following debugging of the previous circuit and correction of the transistor model， the circuit design was then carried out. At 94 GHz， it achieves a gain of 13.7 dB and a noise figure of 3.9 dB. The gain and noise figure are good， but the problem of insufficient linearity needs to be solved.

應用於自旋轉移矩－磁阻式隨機存取記憶體之內建寫入修剪測試及可靠度增強技術;Built-In Write Trimming Test and Reliability-Enhancement Techniques for STT-MRAMs

title: 應用於自旋轉移矩－磁阻式隨機存取記憶體之內建寫入修剪測試及可靠度增強技術;Built-In Write Trimming Test and Reliability-Enhancement Techniques for STT-MRAMs abstract: 自旋轉移力矩磁性隨機存取記憶體（spin-transfer-torque magnetic randomaccess memory， STT-MRAM）是具潛力的嵌入式非揮發性記憶體技術。然而機率性轉態造成寫入可靠度的挑戰，因此需要有效的寫入修剪技術以滿足預期寫入失誤率（write error rate， WER）。本論文第一部分提出一種以外插法為基礎的寫入修剪預測（extrapolation-based prediction write-trimming， EPWT）方法用於選擇可滿足預期WER 的寫入電壓或寫入時間。傳統線性修剪搜尋需要大量取樣才能量測低WER 區域中各個寫入條件所對應的WER，相較之下EPWT 方法使用較少的樣本量測10−3--10−5 範圍的WER，並透過外插選擇低於10−6 預期WER 的寫入條件。相比於線性修剪搜尋，在10 ns 的修剪解析度及不同製程變異程度下EPWT 方法可將測試時間降低約67.7%--69.3%，同時使平均WER維持接近於預期WER 10−6 ，並寫入能量降低0.51%--3.07%。另一方面，驗證後重寫（write-verify-write， WVW）策略可用於判斷寫入操作是否成功。然而使用讀取參考電阻進行驗證時，可能會將陷入中間狀態intermediate state， IM state）記憶體單元判定為寫入成功。IM state 的電阻可能在未施加寫入操作的情況下，隨後復原至平行（parallel， P）或反平行（antiparallel， AP）狀態。若記憶體單元復原至與預期寫入值相反的狀態，儲存位元將發生軟錯誤(soft error)。本論文第二部分提出一種用於驗證之自適應參考電阻的IM state 篩選方法。在生產測試期間，參考電阻修剪機制根據製程變異下觀察到的IM state 電阻分布，調整低、高參考電阻（RL 與 RH）。在WVW 驗證期間，系統根據預期寫入值選擇對應的參考電阻，使IM state 記憶體單元能被辨識為寫入失敗並重新寫入，直到其不再停留於IMstate。相較於使用讀取參考電阻進行驗證，此方法在1% 與5% 製程變異下，平均軟錯誤率（soft error rate， SER）分別降低81.26% 與39.98%。最後，本論文針對STT-MRAM 設計一套可程式化內建自我測試（programmable built-in self-test， PBIST）電路架構，以支援March 測試、讀寫修剪與診斷。此PBIST 採用22 nm ULL CMOS 技術，並以時序100 MHz 的MRAM 進行設計。March測試模組的面積為5，668 μm2，寫入修剪模組的面積則為2，480.44 μm2。;Spin-transfer-torque magnetic random-access memory (STT-MRAM) is a promising nonvolatile memory technology for embedded applications， but its inherent stochastic switching behavior presents write-reliability challenges. Effective write-trimming techniques are therefore essential for satisfying the target write error rate (WER). In the first part of this thesis， an extrapolation-based prediction write-trimming (EPWT) method is proposed to select an appropriate write voltage and/or write time that satisfies the target WER. Instead of using a linear trimming search that requires extensive sampling to measure the WER at each write setting in the low-WER region， the EPWT method measures WERs in the 10−3–10−5 range using fewer samples and extrapolates these measurements to select a write setting for a target WER below 10−6. Compared with linear trimming search， the EPWT method reduces the test time by approximately 67.7%–69.3% while maintaining the final WER near the target of 10−6 under different levels of process variation with a 10 ns trimming resolution. The normalized write energy is also reduced by 0.51%–3.07% at this resolution. On the other hand， a write-verify-write (WVW) strategy can be used to determine whether a write operation has completed successfully. However， verification using a conventional read reference may identify an intermediate (IM) state cell as a successful write. The IM state resistance may subsequently relax to either the P or AP state without an additional write operation. If the cell relaxes to the state opposite to the intended written value， the stored bit becomes incorrect and causes a soft error. In the second part of this thesis， an adaptive verify-reference IM state screening method is proposed. During production testing， a reference-trimming scheme adjusts the low and high reference resistances (RL and RH) according to the observed IM state resistance distribution under process variation. During WVW verification， the appropriate reference is selected according to the intended written value， allowing IM state cells to be identified as write failures and rewritten until they no longer remain in the IM state. Relative to verification using a conventional read reference， the method achieves mean SER reductions of 81.26% at 1% process variation and 39.98% at 5% process variation. Finally， a programmable built-in self-test (PBIST) scheme is developed for STT-MRAM to support March tests， read and write trimming， and diagnosis. The PBIST is designed using 22 nm ultra-low-leakage (ULL) CMOS technology under a 100 MHz MRAM timing constraint. The March test module occupies 5，668 μm2， whereas the write trimming module occupies 2，480.44 μm2