5Gbps 3 倍超取樣眼圖追蹤式時脈資料回復電路 ;5Gbps 3X Over-Sampling Eye-Tracking Clock And Data Recovery Circuit

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/10086

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/10086

Title:	5Gbps 3 倍超取樣眼圖追蹤式時脈資料回復電路;5Gbps 3X Over-Sampling Eye-Tracking Clock And Data Recovery Circuit
Authors:	曾培凱;Pei-kai Tseng
Contributors:	電機工程研究所
Keywords:	眼圖追踨;時脈資料回復電路;over-sampling;eye-tracking;clock and data recovery
Date:	2007-10-03
Issue Date:	2009-09-22 12:06:11 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	隨著製程技術的進步及運算處理速度的提升，傳送接收系統應用在高速上是未來的趨勢，例如應用在乙太網路及光纖網路上規格，如10G Base- LX4、OC-192、OC-768…等。著重在有線或是匯流排上的應用有PCI-EXPRESS、USB2.0、IEEE1394、SERIAL-ATA…等系統，在此系統當中所傳送的資料速度多為Gb/s的等級。高速資料傳送上，有更多的困難需要克服。如雜訊的處理，時脈產生器如何產生高速時脈…等等的問題。本論文採用三倍超取樣眼圖追鎖的技術應用在接收端的時脈資料回復電路上，並以應用PCI-Express II的規格為目標。本論文是應用在5Gb/s的傳送系統的資料接收端的電路上，達到一個高速5Gb/s串列資料。利用鎖相迴路(PLL)作為系統上的時脈產生器，產生5GHz時脈對於輸入的資料作取樣的動作。系統當中需要切割出微小的時脈延遲來調整取樣時脈的相位，採用相位內插的電路利用電流切割方式，切割出6.25ps左右的延遲相位，以達到系統上所規定的頻寬。三倍超取樣的方式可以達到較小的靜態相位誤差，四倍或五倍超取樣的方式複雜度又太大。在整體電路實現上，我們採用0.13-um製程，1.2-V的供應電源來實現接收端的電路。 With the progress in the CMOS process technologies and the operating speed of the processor, high speed links in the transmitter and receiver system are the future tendency . For example, 10Gbase-LX4, OC-192, OC-768 are applied in Gigabit Ethernet and Fiber Channel; PCI-EXPRESS, USB2.0, IEEE1394 and SERIAL-ATA are used in wire or bus serial links. Most of the systems operate at the data rate attending to the level of Gb/s. With the increase of operation frequency, the system design becomes more difficult. These difficulties include noise handling and the generation of the sampling clock at high frequency in receiver side, etc. The thesis adopts 3X over-sampling-eye-tracking techniques in the receiver circuit and tries fit the corresponding specification of PCI- Express II. We designed a receiver circuit which is used in the one serial in data with 5Gb/s and retimed them to a serial 5Gb/sdata. PLL circuit is used as the clock generation circuit and the output clock signals of PLL are used to sample the input data. The small phase delay circuit is implemented by phase interpolator delay to make approximate 6.25ps delay and to tune the phase of sampling clock. A small phase delay is required because of the specification of CDR bandwidth. The reason we adopted the 3X over-sampling is that 2X over-sampling system has larger static phase error and circuit in 4X or 5X is too complex. The receiver system in the thesis is implemented with a 0.13-um CMOS technology with a 1.2V supply power.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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