使用空間相關性分析來探討共質心線段式佈局在運算放器的影響; Spatial Correlation Analysis of Common-Centroid Layout Placement for an OpAmp

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/10272

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Title:	使用空間相關性分析來探討共質心線段式佈局在運算放器的影響;Spatial Correlation Analysis of Common-Centroid Layout Placement for an OpAmp
Authors:	蔡皓州;Hao-Chou Tsai
Contributors:	電機工程研究所
Keywords:	空間相關性;Spatial Correlation
Date:	2008-07-17
Issue Date:	2009-09-22 12:10:25 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	電晶體進入奈米尺寸帶來製程漂移、參數劇烈變動，導致良率更難以評估。在SPICE電路模擬分析時，往往將元件參數彼此間的變動視為獨立的；然而電路在晶圓廠製造過程中，元件彼此間的參數變動是有關聯性的。所以，加入相關性概念的電路模擬更能客觀與準確預測電路特性。因為在實際佈局上，常運用多線段電晶體的擺放來降低不匹配效應。故本論文導入相關性變動探討多線段電晶體對雙級放大器的影響。並觀察Common-Centroid佈局抑制參數變動的效果。最後提出一種方法來排除大量元件模擬上的限制。 While the critical dimension of transistors gets in advancement to nano-meter, it will bring the drift for larger parameter variability in manufacturing process, and is more difficult to evaluate the yield. In SPICE simulation, it treats the parameter for each same-type device as identical. Therefore we could not know the mismatch between devices. However, the parameter variation of each device should have certain correlation during manufacturing process. Taking the correlation into the simulation, it would be more objective and accurate for predicting the circuit performance. Segments of devices are widely used in physical implementation for reducing the mismatch. A two-stage OPA is used to analyze the effect of device correlation and it is observed that how the mismatch is suppressed in Common-Centroid layout.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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