隨著半導體製程技術進入深次微米時代，製程變動對於電路效能的影響愈來愈嚴重。因著製程變動已被觀察到存在著空間相關性，我們需要高速且可考慮製程變動相關性的方法使得我們可以更準確的估計電路效能參數的變動並且減少設計疊代成本。我們提出一個可計算類比電路各階層參數變異數之高速階層變異數分析方法的延伸架構，使之可考慮製程變動的相關性。我們提出兩個方法來實現這個分析器：1) 在製程層下建構一個虛擬層，以及2) 在原本的統計模型上加上第二個修正項。實驗結果顯示任一種方式實現出來的分析器皆達到出色的精準度及效率。 As the technology scales down to ultra-deep-submicron, the impact of process variations on circuit performance gains importance. For it has been observed that the process variations are spatially correlated, analysis with the consideration of process parameters correlations and high computational efficiency is needed to help estimating variations of circuit performance accurately and reducing the cost of design iteration. We present an extended scheme of a prior high speed hierarchical variance analysis method to calculate the variance of parameters at each hierarchical layer in analog circuits while taking process parameters correlations into account. The proposed analyzer is realized by two ways: 1) constructing an extended pseudo level below process-layout level and 2) adding a second correction term to the prior statistical model. Experiment results show that analyzer realized by either of the two ways achieves high computational accuracy and efficiency.
