隨著積體電路(IC)的研發技術演進，製程尺寸進入了奈米(nanometer)技術時代。當製程技術不斷地推陳出新，製程變異(process variation)對於電路效能的影響也日益嚴重，進而導致生產良率(yield)大幅下降。有鑑於此，針對積體電路的製造可行性設計(Design for Manufacturability, DFM)或良率導向設計(Design for Yield, DFY)，成為近年來十分熱門的研究議題。主要的概念，是希望在電路設計初期，把製造過程中可能產生的製程變異現象考慮進來，事先評估對電路效能的影響；若分析之良率不佳，及早在設計初期改良電路。這樣不但能達到提升良率的效果，還能減少重新設計或重新下線(Re-spin)的時間，大幅降低IC設計成本。 設計中心化(design centering)，是一種最常被使用在良率優化的技術。主要以初始電路的標稱設計(nominal design)，經過良率分析與良率優化的步驟，將標稱設計點逐步移動，使得大多數的模擬樣本點均落在允許之設計區間(acceptable design region)之中，以提升設計良率。然而，在傳統設計中心化的演算法中，需要以大量的設計限制及繁複的數學公式，來定義出可行性參數區間的邊界；對於較複雜的類比電路而言，要定義出合理的可行性參數區間之邊界，實屬不易。 本論文是針對製程變異敏感(sensitive)的類比電路，以最常用的鎖相迴路(PLL)為研究實例，提出一套有效率的良率優化方法，有別於過去的研究，本論文無須定義複雜的可行性參數區間之邊界，而是透過既有的效能模擬結果，再利用統計分析的結果與力學模型的輔助，找出改善良率之設計標稱點位置；然後，將電路依照其階層高低，逐層調整其參數以修正電路設計，達到提升良率的目的。換言之，這種無邊界式的良率優化方法，在不需要描繪可行性參數區間之邊界的前提下，即使是面對複雜的類比電路，也能夠有效率地去修正設計標稱點，達到良率優化的目的。 With the shrinking device size in deep submicron process, the process variation influence on circuit performance is more and more serious, especially for analog circuits. Therefore, design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have become popular research directions in recent years. The main concept of DFM and DFY is to consider the process variation effects in early stage of IC designs. If we can evaluate the impacts of circuit performance under process variations in advance, the circuit yield could be improved at early stages to reduce the re-design cycles and re-spin cost. Design centering is one of the popular techniques for yield enhancement. Using the nominal design as an initial point, this technique gradually moves the nominal point toward better yield by using the results of circuit performance analysis so that most of simulation samples under process variations will locate in acceptable design regions. However, traditional design centering approaches often require complicated formulas and numerous design constrains to find out the boundaries of acceptable design regions. For complicated analog circuits, such approaches may be difficult to figure out the borders of feasible regions for yield enhancement. In this thesis, a boundary-less design centering approach is proposed for phase- locked-loop (PLL) circuits, which are very sensitive to process variations. Instead of finding the borders of feasible regions, this work searches the moving tracks of nominal points by reusing the yield analysis results and some mechanics models. After finding the nominal point with better yield, the original design will be adjusted hierarchically to match that nominal point and generate a highly-reliable circuit. Because the proposed yield enhancement approach does not need the complex process to find the boundaries of feasible regions, complicated analog circuits like PLL can also be handled efficiently. As demonstrated in the experimental results, this work indeed improves the design yield of a PLL in a short time even though the PLL circuit is so complicated.
