在現今的系統晶片(System on a Chip; SoC)設計的時代，為了要縮短設計的時間，以期提升系統晶片設計的可靠度與效能，便希望能在設計初期就能夠知道每一個區塊的電流資訊，如此不只可以及早作功率的最佳化，對於電源線的設計與佈局來說，也能預先考慮到SSN (Simultaneous Switch Noise) 和IR-drop這類雜訊的影響，因此高階電流模型一直以來都是備受重視的研究領域，因為在使用上不需要知道內部電路的資訊，就可以快速的得到電路區塊的電流波形，也使得在應用上非常方便。 因此本篇論文針對嵌入式記憶體提出了一個高階電流模型，先利用萃取的輸入向量對（Extraction Pattern Pairs）進行HSPICE的模擬，進而得到所有電路中電流波形和輸入輸出轉態情況的關係，並合併相同處理程序的輸入輸出狀況來降低電流模型的複雜度，接下來就可以利用建立好的高階電流模型的輸入向量與其相對應電流波形之間的關係，並配合論文中提出的方法流程，可以針對不同的記憶體架構建構個別的電流模型，且在模型建好之後，能夠同時對不同形狀的電流波形做估計，可說是非常方便有效率。 In system-on-a-chip（SoC） era, the current information of the circuits is required in the early design stages to improve the performance and reliability of the designs. With the current information, designers can optimize the power consumption, design proper power lines and layout, and take care of the noise effects, such as simultaneous switch noise（SSN）and IR-Drop. Therefore high-level current models also play an important role in SoC design flow. Because the detailed information inside the current is not required while using high-level current models, it is convenient to quickly obtain the current waveform of a circuit from current models. In this thesis, we propose a high-level current model for embedded memories. Using the special designed extraction patterns all possible current waveforms cab be obtained from HSPICE simulation. By merging the current waveforms generated from similar operations into one model, the complexity of the proposed model can be reduced. Then, the relationship between current waveforms and input/output vectors for each kind of current models is stored in a file for future estimation. For the current waveforms with different shapes, we propose different templates to record them efficiently. As demonstrated in the experiments, this approach is indeed a convenient and efficient method to estimate the current waveforms of embedded memories.
