正交分頻多工(OFDM)技術，提供了抗多路徑干擾與高頻譜效率的特性，因此被廣泛地應用在許多無線通訊系統中。在正交分頻多工系統中，快速傅利葉轉換處理器是其中一個高運算複雜度的模組，在系統中佔了很大功耗比例。因此應用於無線可攜的正交分頻多工系統中，一個低功耗的快速傅利葉轉換處理器便可增加裝置的使用時間。多數正交分頻多工通訊系統都須支援多種點數的快速傅利葉轉換，並且目前一些通訊標準已加入多路徑輸入多路徑輸出(MIMO)技術，因此本論文提出一個可支援多系統標準，且具低功耗及可變長度彈性MIMO的快速傅利葉轉換處理器。在我們的快速傅利葉轉換處理器設計中，因為可彈性地組合變化支援的點數長度與MIMO資料串數，使得記憶體在不同點數下有最佳的使用率。在降低功率消耗與硬體成本設計考量中，我們利用最佳化字元長度可節省128K位元的記憶體，利用適當的排程可使用單埠的記憶體，並使用乒乓快取記憶體架構最多可將一半的記憶體存取轉移到較小的快取記憶體上。最後我們使用TSMC 0.18 μm製程實現支援多系統1024、2048、4096與8192點彈性MIMO的快速傅利葉處理器，晶片核心面積為4.91mm2。單一路徑8192點模式操作在10MHz下，功率消耗約為20.48mW。 Recently, orthogonal frequency-division multiplexing (OFDM) technique has been widely applied in many wireless communication systems due to the multi-path immunity characteristic and high spectrum efficiency. In the OFDM systems, fast fourier transform (FFT) processor is a module requiring high processing complexity. The overwhelming majority of the system power is consumed by such a module. As a result, an FFT processor with low power dissipation can be used to effectively extend the lifespan of the OFDM-based portable devices. Most of the OFDM systems so far support multi-point FFT and certain of them have been with the multi-input multi-output (MIMO) technique. In this thesis, a low-power and variable-length FFT processor is proposed for flexible MIMO-OFDM applications. The memory involved in the proposed FFT processor can provide with a best utility rate as it has been designed to allow variable combinations of the FFT size and numbers of input and output sequences in MIMO system. On the considerations of reducing power dissipation and hardware implementation overhead, a scaling method has been proposed to save the memory up to 128 Kbits by properly scheduling the available single-port memory and using ping-pong cache architecture. Designed in a TSMC 0.18-um process, the proposed design can support 1024, 2048, 4096, and 8192 points for flexible MIMO applications. The proposed design can support 1024, 2048, 4096, and 8192 points for flexible MIMO applications, and is fabricated in a 0.18-μm CMOS technology. The core area of the proposed FFT processor is 4.91 mm2. Under an 8192-point Serial-input Serial-output (SISO) mode, the power dissipation of the proposed FFT processor is 20.48 mW at 10 MHz clock rate.
