現今VLSI製程技術已進入了奈米(Nanometer)的時代，使得電源完整性(Power Integrity)的問題成為限制電路效能原因之一。傳統上，要得到準確的電流波形須要到電晶體階層(Transistor level)做模擬才能得知，所以要到設計流程的後段才能去檢查電源完整性，因此，我們提出了使用動態階級化演算法(Dynamic levelization algorithm)之高階電流模型。動態階級化考慮了輸入向量以及對應的電流波形，把電路中的邏輯閘各分配到適當的Level來簡化電路複雜度，將各個Level的電流波形利用離散餘弦轉換(Discrete cosine transform)由時域波形轉為規律的頻域波形來處理。只需要一個模型，就可以估測不同形狀的電流波形，像是三角形波、梯形波亦或是多峰值波形，當模型建立好後，不須任何的手動調整，便可利用此模型來估測任意輸入向量所對應的電流波形。而實驗結果也證明，我們的高階電流模型確實可以產生足夠準確、相似度逼近電晶體階層的電流波形，提供使用者可以在設計初期做初步的雜訊估測。 As VLSI technology goes into nanometer era, the power integrity problem becomes one of the critical issues that limit the design performance. Traditionally, accurate supply current waveform can only be obtained from transistor-level simulation. Power integrity check is mostly performed at very late design stage in current design flow. Therefore, a high level current model for logic blocks using dynamic levelization algorithm is proposed to solve this problem. Proposed dynamic levelization algorithm can simplify the waveform complexity by grouping the gates by their logic level. Then, levelized current waveforms are transformed by DCT to obtain regular frequency domain waveforms. Thus, any shapes of current waveforms like triangular, trapezoidal, or multi-peak waveforms can be estimated by the proposed model without any manual tuning and extra information except the input/output values. Finally, the experimental results prove proposed that high-level current model provide accurate enough supply current waveforms for noise analysis at early design stages.
