由於視訊技術不斷地演進，對於視訊解析度和品質的要求也越來越高，儲存或傳送時進而產生了大量的視訊資料。要使如此大量資料量的影像應用實現，則必須使用到視訊編碼技術。MPEG-4 AVC/H.264是近期提出的編碼規格，跟其他規格相比，它的效能是最好的。然而，要實現一個H.264編/解碼器，我們會碰到高運算複雜度的瓶頸。 為了解決這個問題，此篇論文揭露了先進的適應性二元算術編碼及運動補償硬體架構設計使用於H.264編/解碼器。我們最佳化二元算術編碼及運動補償的硬體架構─它們同時也是整個H.264編/解碼器最需要大量運算及複雜的模組，已達到理想的性能。 在二元算術編碼設計中，我們提出一個無衝突多符號算術編碼器。多符號算術編碼器的產出率通常被同時對背景作存取所限制，降低整個H.264編碼器的性能。利用提出的混合式背景記憶體架構，在2-符號和4-符號的版本中，產出率分別提升了15%和55.5%。實現結果跟其他參考資料比較，也顯示硬體設計可以達到高產出率和編碼率。 此外，我們提出一個高硬體使用率、低頻寬需求的4x4區塊階層管線運動補償架構。利用提出的最小化參考資料讀取和資料重複使用方法，頻寬減少了70%，同時不違背H.264固有的double-z掃描順序。我們進一步最佳化運動補償中的有限脈衝響應和晶片記憶體，已達到較佳的硬體使用率和解碼時間。提出的運動補償硬體可支援1920x1088 30fps 4x4區塊階層管線的H.264解碼器，使用低於60MB/s的頻寬和432-byte的晶片記憶體，操作在100MHz。 With the progress of video technology, the demands of large resolution and high quality for a video sequence introduce large amount of video data while storing or transmitting. The key role of making the video application possible along with tremendous data is video coding techniques. In the recent development, MPEG-4 AVC/H.264 is the latest video coding standard which output performed the others. However, the high computational complexity of a H.264 CODEC (enCOder/DECoder) is a bottleneck to implement it. In order to solve this challenge, the novel hardware architecture designs of context-based adaptive binary arithmetic coding (CABAC) and motion compensation (MC) for a H.264 CODEC are presented in this thesis. The hardware architectures of CABAC and MC, which are the most computational cost and complexity modules in whole CODEC, are optimized in order to reach the expected performance. A conflict-free multi-symbol arithmetic encoder (AE) is proposed in our CABAC design. The throughput of a multi-symbol AE is usually limited by concurrent access of context memory which degrades the performance of the whole H.264/AVC encoder. With proposed Hybrid Context Memory architectures (HCM), the number of encoding symbol per cycle is improved by 15% and 55.5% in 2-symbol and 4-symbol version, respectively. The implementation results also show that the hardware design can achieve a high encoding rate and throughput comparing to the previous works. Moreover, a 4x4-block level pipeline MC architecture for H.264/AVC decoder with high hardware utilization and low bandwidth requirement is presented. With the proposed Minimum Required Reference Data Loading (MRRD) and Data Reuse from Upper/Left block (DRUL) strategies, the memory bandwidth is reduced by 70% without violating the inherent double-z-scan order of H.264/AVC bitstream. The FIR filters and the on-chip memory in MC is further optimized to improve hardware utilization and decoding time. The proposed MC hardware can support 1920x1088 30fps 4x4-block level pipeline in H.264/AVC decoder with less than 60MB/s memory bandwidth and a 432-byte on-chip memory when operating at 100MHz.
