Ku/K頻段壓控振盪器及注入鎖定除頻器暨毫米波fT-倍頻電路壓控振盪器與寬頻混頻器之研製; Ku/K Band Voltage Controlled Osillator, Injection Locked Frequency Divider, and Millimeter-Wave Voltage Controlled Oscillator, Broadband Mixer Using fT-Doubler Technique

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題名:	Ku/K頻段壓控振盪器及注入鎖定除頻器暨毫米波fT-倍頻電路壓控振盪器與寬頻混頻器之研製;Ku/K Band Voltage Controlled Osillator, Injection Locked Frequency Divider, and Millimeter-Wave Voltage Controlled Oscillator, Broadband Mixer Using fT-Doubler Technique
作者:	陳瑋強;Wei-Ciang Chen
貢獻者:	電機工程研究所
關鍵詞:	次諧波混頻器;傳輸線耦合器;本質接面電容;轉導提升;fT倍頻器;注入鎖定除頻器;壓控振盪器;相位雜訊;脈衝靈敏函數;變壓器;雜訊濾波器;寬頻混頻器;gm-boosted;injection-locked frequency divider;transformer;impluse sensitive function;phase noise;voltage controlled oscillator;broadband-mixer;transmission line coupler;fT-doubler;intrinsic capacitor;noise filting;sub-harmonic mixer
日期:	2009-07-06
上傳時間:	2009-09-22 12:15:38 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	本論文主要包含兩者主題，第一設計Ku頻段之本振訊號生成電路，包含壓控振盪器與注入鎖定除頻器，及K頻段之省面積壓控振盪器。第二使用fT-倍頻電路設計毫米波壓控振盪器及寬頻混頻器及寬頻次諧波混頻器。以上電路分別係使用TSMC 0.18 μm與TSMC 0.13 μm CMOS製程完成設計。第一部分為Ku/K頻段之振幅分佈式壓控振盪器，以線性時變系統觀點分析此壓控振盪器之相位雜訊生成機制，並探討電壓限制與電流限制對此壓控振盪器之影響。電路架構上以雙共振腔增加閘極振幅來提升交錯耦合對電晶體之訊雜比，降低電晶體本身熱雜訊，進而減少相位雜訊中之電流雜訊功率頻譜密度，並手算分析在控制電壓變化下之雜訊分佈，與模擬與量測作驗證。使用TSMC 0.18 μm製程技術來實現此三位元切頻振幅分佈式壓控振盪器，振盪中心頻率為12.8 GHz，可調頻寬為720 MHz，且在供應電壓為1.2 V，功率消耗為6.4 mW下，於偏移頻率1 MHz時，相位雜訊為-114.83 dBc/Hz，計算優化指標為-188.93 dBc/Hz，晶片面積為0.54 mm2。考慮到使用雙共振腔造成面積上的損耗，係使用TSMC 0.13 μm CMOS製程技術來實現K頻段不等Q值變壓器之振幅分佈式壓控振盪器，設計一變壓器來減少雙共振腔面積，使用不等Q值電感設計方式來同樣達到振幅分佈之功效。振盪中心頻率為25 GHz，可調頻寬為900 MHz，且在供應電壓為1.2 V，功率消耗為5.82 mW下，於偏移頻率1 MHz時，相位雜訊為-107.16 dBc/Hz，計算優化指標為-187.6 dBc/Hz，晶片面積為0.02 mm2。第二部分係使用TSMC 0.18 μm CMOS製程技術實現轉導提升注入鎖定除頻器設計。藉由架構與偏壓選擇，來達到低功率消耗且寬頻鎖定之特性。在供應電壓為1.8 V，功率消耗為3.78 mW下，鎖定頻寬範圍11~14.4 GHz達26.7 %以上，計算優化指標為7.36 %/mW，晶片面積為0.415 mm2。第三部分為毫米波壓控振盪器，其中包含三種電路架構，同時以fT-倍頻電路作為設計核心。首先針對fT-倍頻電路作分析，係以第一種分析法應用在壓控振盪器設計上，具有低功率消耗及低相位雜訊之特性。架構一操作頻率為74 GHz，可調頻寬達1110 MHz以上，在供應電壓為1.2 V，功率消耗為12.38 mW下，於偏移頻率10 MHz時，相位雜訊為-114.7 dBc/Hz，計算優化指標為-181.2 dBc/Hz，晶片面積為0.012 mm2。架構二加入本質接面電容作可調電容設計，操作頻率為65 GHz，可調頻寬225 MHz以上，在供應電壓為1.5 V，功率消耗為9 mW下，於偏移頻率10 MHz時，相位雜訊為-102.8 dBc/Hz，計算優化指標為-169.6 dBc/Hz，晶片面積為0.024 mm2。架構三加入尾部電流源加入雜訊濾波電路及設計一高Q值μ型傳輸線作為共振腔及雜訊濾波電感。操作頻率為58.5 GHz，可調頻寬2590 MHz以上，在供應電壓為1.2 V，功率消耗僅5 mW下，於偏移頻率10 MHz時，相位雜訊為-121.8 dBc/Hz，計算優化指標為-190.1 dBc/Hz，晶片面積為0.02 mm2。第四部分為毫米波寬頻混頻器，以低損耗平面式90o藍基耦合器補償電晶體fT之損耗，設計一寬頻、低功耗及高轉換增益之主動式單端寬頻混頻器。其量測結果在使用TSMC 0.18 μm CMOS製程下，供應電壓為1.8 V，功率消耗為9.54 mW下，操作頻率範圍7~67 GHz，轉換增益為4.6±1 dB，LO-IF隔離度大於30 dB，，P1dB壓縮點為-2 dBm，整體面積為0.5 mm2。在使用TSMC 0.13μm CMOS製程下，供應電壓為1.8 V，功率消耗為18 mW下，操作頻率範圍4.5~67 GHz，轉換增益為6.7±1.3 dB，LO-IF隔離度大於37 dB， P1dB壓縮點為1 dBm，整體面積為0.15 mm2。為了改善隔離度，設計一次諧波混頻器，以功率分配器與馬遜平衡器饋入射頻與本振訊號，在供應電壓為1.8 V，功率消耗為13.7 mW下，操作頻率範圍35~64 GHz，轉換增益為0±2 dB，各埠隔離度大於30 dB， P1dB壓縮點為2 dBm，整體面積為0.71 mm2。 The content of this thesis consists of six chapters. Two types RF and mm-wave circuits will be investigated in this thesis. The first one is an LO generation of Ku-band system, include voltage controlled oscillator (VCO) and injection locked frequency divider (ILFD), and a compact VCO for K-band system. The other one is millimeter-wave VCO, broadband mixer, and broadband sub-harmonic mixer using fT-doubler cell, which are implemented in TSMC 0.18-μm and TSMC 0.13-μm CMOS technologies, respectively. Chapter two presents Ku/K-band voltage controlled oscillators with amplitude redistribution technique. The linear time-varying system concept is used to analyze the phase noise causing, and discuss the effect of the voltage limit and current limit of the VCO topology. The VCO is implemented by the bi-resonator to enhance the amplitude at the gate terminal of the cross couple pairs, which also increases the signal-to-noise ratio (SNR) to suppress the noise current injected to resonator, also decreases the power spectrum density on the phase noise, simultaneously. The analysis results are verified by hands-on calculation, circuit simulation, and measurements. A 3-bit band-switching amplitude redistribution VCO was implemented in TSMC 0.18-μm CMOS technology. The obtained oscillation frequency is 12.8 GHz, with a tuning range of 720 MHz under the supply voltage of 1.2 V. The power consumption is 6.4 mW. The measured phase noise is -114.83 dBc/Hz at 1-MHz offset frequency. The figure-of-merit (FoM) is -188.93 dBc/Hz. The total chip size included the test pads is 0.54 mm2. An un-equal Q value of transformer architecture, instead of bi-resonator, is proposed to save chip area. The un-equal Q transformer with amplitude redistribution VCO was implemented in TSMC 0.13-μm CMOS technology. The center frequency is 25 GHz with the tuning range of 900 MHz under the supply voltage of 1.2 V. The power consumption is 5.82 mW. The measured phase noise is -107.16Bc/Hz at 1-MHz offset frequency. The figure-of-merit (FoM) is -187.6 dBc/Hz. The core area of this VCO is only 0.02 mm2. Chapter three presents a Gm-boosted injection-locked frequency divider (ILFD) applied in Ku-band system. This ILFD circuit was implemented in TSMC 0.18-μm CMOS technology. The ILFD provides a wide locking range under low power dissipation through Gm-boosted VCO topology with the proper choice the bias point of injection transistor. The operating frequency is 11-14.4 GHz (>26.7%) under the supply voltage of 1.8 V. The power consumption is 3.78 mW. The calculated figure-of-merit is up to 7.36 %/mW. The total chip size included the test pads is 0.415 mm2. Chapter four presents three types of millimeter-wave VCO using the fT-doubler cell. The fT-doubler cell is analyzed and applied to VCO designs, which perform low power dissipation and low phase noise. The VCO design using topology I can operate up to 74 GHz with the tuning range of 1100 MHz under a supply voltage of 1.2 V. The power consumption is 12.38 mW. The measured phase noise is -114.7 dBc/Hz at 10-MHz offset frequency. The calculated FoM is -181.2 dBc/Hz. The core area is only 0.012 mm2. The VCO design using topology II combines with the intrinsic capacitor to vary the operation frequency. The obtained center frequency is 65 GHz with a tuning range of 225 MHz under the supply voltage of 1.5 V. The power consumption is 9 mW. The measured phase noise is -102.8 dBc/Hz at 10-MHz offset frequency. The calculated FoM is -169.6 dBc/Hz. The core area is only 0.024 mm2. The VCO design using topology III modifies the fT-doubler cell to improve the phase noise for a noise filter and design a high Q μ–micro stripline to instead the inductor of resonator. The center frequency is 58.5 GHz with a tuning range of 2590 MHz under the supply voltage of 1.2 V. The power consumption is 5 mW. The measured phase noise is -121.8 dBc/Hz at 10-MHz offset frequency. The calculated FoM is -190.1 dBc/Hz. The core area is only 0.02 mm2. Chapter five presents millimeter-wave broadband mixers using fT-doubler cell. The novel active single-ended mixer provides broadband, low power dissipation, and high conversion gain performance. The RF signal of mixer feeds in the through port of the Lange coupler to compensate the fT decrease of the fT-doubler cell against the frequency. The first one fT-doubler mixer was implemented in TSMC 0.18-μm CMOS technology with excellent performance. The operating frequency range of the mixer is 7~67 GHz under the supply voltage of 1.8 V. The power consumption is 9.54 mW. The conversion gain is 4.6±1 dB with the OP1dB of -2 dBm. The isolation of LO-IF, LO-RF, and RF-IF was better than 11 dB. The compact core chip area is 0.5 mm2. The second fT-doubler mixer was implemented in TSMC 0.13-μm CMOS technology. The single-ended mixer obtains the measured conversion gain of 6.7±3 dB from 4.5~67 GHz under the supply voltage of 1.8 V. The power consumption is 18 mW. The isolation of LO-IF is better than 30 dB. The measured OP1dB is 1 dBm. The core chip area is 0.15 mm2. To improve the isolation, a novel sub-harmonic mixer combines with a power divider and a stacked Marchand balun to input the signals of RF and LO. This broadband sub-harmonic mixer achieves a conversion gain of 0±2 dB from 35 to 64 GHz under the supply voltage of 1.8V. The total power dissipation is 13.7 mW. The measured isolations of LO-IF and LO-RF are better than 32 dB, RF-IF isolation is better than 44 dB. The measured OP1dB is 2 dBm. The core chip area is 0.71 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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