部分平行低密度同為元檢查碼解碼器設計; A Partially Parallel Low-Density Parity Check Code Decode

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/10473

Title:	部分平行低密度同為元檢查碼解碼器設計;A Partially Parallel Low-Density Parity Check Code Decode
Authors:	吳佳俊;Chia-chun Wu
Contributors:	電機工程研究所
Keywords:	低密度同位元檢查碼解碼設計;檢查碼;Low-Density Parity Check Code Decode;LDPC
Date:	2009-07-20
Issue Date:	2009-09-22 12:18:33 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	摘要 LDPC解碼演算法是使用訊息傳遞(Message passing)；要獲得高效率的解碼情況下，在解碼硬體實現上必須使用大量的記憶體來儲存交換的訊息，而所需的記憶體大小跟同位元矩陣(H matrix)中1的數目有關。換句話說，當同位元矩陣架構越大的話則所需要的記憶體也會增加。部分平行架構的兩種記憶體使用方法，共享記憶體架構與獨立型記憶體架構已普遍實施於LDPC解碼器。過去的研究提出了一種替代的方法，大大減少了記憶體大小的需求。在本論文中，提出使用移位暫存器用來取代記憶體，並以資料取回電路，進一步提高吞吐量。結果顯示，本論文LDPC碼解碼器，在碼長為1536和編碼率為1 / 2，頻率為380MHz時吞吐率可達到124 Mbps。 Abstract LDPC decoding algorithm is a result of the use of Message passing Concept way, obtain efficient decoding circumstances, the realization of the decoder hardware, with plenty of memory to store the messages exchanged, required memory size with the same H matrix contains the number of 1. In other words, When the H Structure, then the greater the need will increase memory. Two partially parallel architectures have been commonly implemented for LDPC decoders: Share-memory architecture and Individual-memory architecture. Our previous study has presented an alternative approach that significantly reduces the memory size requirement. In this study, shift-registers are employed to replace memory to simplify the data retrieval scheme and to further improve the throughput. Results show that the a LDPC decoder, with a code length of 1536 and a code rate of 1/2, can achieves the data rate up to 166 Mbps at the maximum clock frequency of 460 MHz.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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