A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver

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题名:	A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver
作者:	邱煥凱;Chiou, Hwann-Kaeo;Lin, Kuei-Cheng;Chen, Wei-Hsien;Juang, Ying-Zong
贡献者:	資訊電機學院電機工程學系
关键词:	AC coupling;Amplifiers;CMOS;current reuse;direct-conversion receiver;double balanced mixer;Electric potential;folded-switch mixer;Intermodulation;low voltage;Mixers;MOSFETs;Noise;Noise levels;Radio frequency;Receivers;Topology;Transconductance;Wireless communication
日期:	2012-01-01
上传时间:	2026-04-23 13:14:33 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:	摘要： A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP 3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP 2 ) and IIP 3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP 2 and the IIP 3 of the DCR are 33 dBm and -12 dBm, respectively. 其他題名： TCSI 出版者： New York: IEEE 出版日期： 2012-06-01 出處： IEEE transactions on circuits and systems. I, Regular papers, 2012-06, Vol.59 (6), p.1215-1227 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jun 2012 識別號： ISSN: 1549-8328 識別號： EISSN: 1558-0806 識別號： DOI: 10.1109/TCSI.2011.2173399 識別號： CODEN: ITCSCH
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