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    請使用永久網址來引用或連結此文件: https://ir.lib.ncu.edu.tw/handle/987654321/106326


    題名: A dual-gate 2nd/3rd-order subharmonic injection-locked oscillator in GaAs PHEMT
    作者: 辛裕明;Huang, Fan-Hsiu;Hsin, Yue-Ming
    貢獻者: 資訊電機學院電機工程學系
    關鍵詞: Circuits;Dual-gate;Enhanced/depletion-mode PHEMT;Gallium arsenide;Gallium arsenides;Injection locked oscillator;Locking;Oscillators;Silos;Subharmonic injection locking;Tuning;Wideband
    日期: 2014-01-01
    上傳時間: 2026-04-23 13:17:50 (UTC+8)
    出版者: Elsevier BV;Elsevier Ltd
    摘要: 摘要: A dual-gate subharmonic injection-locked oscillator (SILO) has been designed and fabricated in 0.5μm GaAs PHEMT process for millimeter-wave communication applications. Specifically, this study proposes a dual-gate circuit topology to achieve a high-frequency oscillator with a large output signal power. The proposed dual-gate transistor also performs a wideband negative resistance characteristic by which the self-oscillation frequency can easily be determined with a proper resonator. The measured self-oscillation frequency of the proposed SILO is approximately 49GHz, and the frequency tuning range is adjustable from 48.7GHz to 49.7GHz with an output power of 8dBm. By injecting a 2nd-order (~24.5GHz) subharmonic signal into the dual-gate SILO, the maximum locking range of 5.6GHz can be approached at an input power of 11dBm without any self-oscillation frequency tuning. With changing the input frequency to be a 3rd-order subharmonic injection (~16.3GHz), an output locking range of 2.9GHz also can be achieved. The measured phase noises of the output signals from 2nd- and 3rd-order subharmonic injections are −101 and −100dBc/Hz, respectively, at 100-kHz offset frequency.
    出版者: Elsevier Ltd
    出版日期: 2014-01
    出處: Microelectronics, 2014-01, Vol.45 (1), p.89-94
    版權: 2013 Elsevier Ltd
    識別號: ISSN: 1879-2391
    識別號: ISSN: 0026-2692
    識別號: DOI: 10.1016/j.mejo.2013.10.005
    顯示於類別:[電機工程學系] 期刊論文

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