Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:
摘要： In this brief, a power-efficient multiple-input multiple-output (MIMO) detector that can flexibly support multiple antenna configurations and modulations is presented. This detector uses a sorting-free K-best algorithm named distributed K-best (DKB) algorithm and successive interference cancellation (SIC) to decrease computational complexity. The DKB and SIC schemes are designed as several elementary building blocks. Then, the antenna configurable architecture can be flexibly constructed by these elementary blocks. The multistage hardware architecture is proposed to achieve that only K clock cycles are required to find out the best K candidates, and the sorting circuit for the conventional K-best algorithm is avoided in our design. In addition, a shift multiplier which simply uses bit shift and additions is applied to replace the conventional multiplier for further reducing power consumption. The proposed configurable MIMO detector has been fabricated in 90-nm CMOS technology with core area of 0.7744 mm 2 . For 8 × 8, 64-QAM, and K = 10 configuration, the proposed chip achieves 489-Mb/s throughput rate with 17-mW power consumption at 102-MHz operating frequency and 1 V supply voltage. The performance results show that the proposed design has better power efficiency and antenna configurability than other related works. 其他題名： TVLSI 出版者： New York: IEEE 出版日期： 2014-11-01 出處： IEEE transactions on very large scale integration (VLSI) systems, 2014-11, Vol.22 (11), p.2418-2422 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nov 2014 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2013.2288574 識別號： CODEN: IEVSE9
