隨著半導體製程尺寸逼近原子尺度，傳統矽基材料面臨嚴峻的短通道效應與漏電挑戰，二維材料因具備原子級厚度與優異的靜電控制能力，成為突破摩爾定律的關鍵材料。在眾多過渡金屬二硫屬化物中，二硫化鉬(MoS2) 因其高環境穩定性與合適的能隙脫穎而出 。然而，傳統化學氣相沉積法（Chemical Vapor Deposition，CVD）在無圖案化基板上成長時常伴隨隨機成核與多層堆疊，難以精密控制成核位置與晶體形貌。 本研究分為兩個主要階段。第一階段聚焦於低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition， LPCVD）生長單層MoS2之參數優化，系統性調控反應溫度、系統壓力、氣體流量與前驅物比例。實驗結果顯示，當鉬源(MoO3)劑量為25 mg且加熱至 790°C、系統壓力25 Torr、氬氣流量 80 sccm，並搭配700 mg 硫粉且硫源提前反應2分鐘，為最佳生長條件。此參數成功平衡了前驅物之質傳與表面擴散速率，可穩定獲得結晶品質優異、光致發光（PL）半高寬最優為75.68 meV且尺寸達28 µm 的正三角形單層單晶。第二階段則引入圖案化石墨烯輔助生長基板，利用微影與電漿蝕刻定義出石墨烯邊界，引導MoS2定向側向生長。為調控界面化學活性，研究對比了Ar/ H2 與引進氨氣的雙階段Ar/ H2+Ar/NH3退火處理。結果證實，在降低鉬源至15 mg的基礎下，單純使用 Ar/ H2退火在不同通道寬度下易呈現雙層結構，無法精準控制層數。相較之下，經由雙階段Ar/ H2+Ar/NH3高溫退火的樣品，D band增高且2D band下降，顯示石墨烯表面存在較多缺陷之活性位點，有利於前驅物的吸附與成核。此機制有效抑制了垂直堆疊，在2 µm至30 µm的通道寬度下，均能穩定重現結構均勻的單層MoS2連續膜。 最後，在元件評估方面，研究發現石墨烯與藍寶石基板在經歷高溫製程後具備極強的界面鍵結力，導致傳統濕式轉印法面臨材料破損與層間斷裂之瓶頸。為規避轉印損耗，本研究直接於原始藍寶石基板上製備出頂閘極場效電晶體（Top-gate FET），順利確保了元件電學傳輸特性評估的可行性，為未來低接觸電阻之二維半導體界面工程提供了極具價值的製程指導方針。;As semiconductor technology approaches the atomic scale， conventional silicon-based materials face severe challenges associated with short-channel effects and leakage current. Owing to their atomic thickness and excellent electrostatic control， two-dimensional (2D) materials have emerged as promising candidates for extending device scaling beyond the limits of Moore’s law. Among various transition metal dichalcogenides (TMDCs)， molybdenum disulfide (MoS₂) has attracted considerable attention because of its high environmental stability and suitable bandgap. However， conventional chemical vapor deposition (CVD) on unpatterned substrates typically suffers from random nucleation and multilayer stacking， making it difficult to precisely control nucleation sites and crystal morphology. This study consists of two major stages. The first stage focuses on optimizing the growth parameters for monolayer MoS₂ using low-pressure chemical vapor deposition (LPCVD). The reaction temperature， chamber pressure， carrier gas flow rate， and precursor ratio were systematically optimized. The experimental results indicate that the optimal growth condition was achieved using a 25 mg MoO₃ precursor heated to 790 °C， a chamber pressure of 25 Torr， an Ar flow rate of 80 sccm， and 700 mg of sulfur powder with sulfur introduction initiated 2 minutes prior to growth. Under these conditions， a balance between precursor mass transport and surface diffusion was achieved， resulting in high-quality equilateral triangular monolayer MoS₂ single crystals with a minimum photoluminescence (PL) full width at half maximum (FWHM) of 75.68 meV and an average crystal size of 28 μm.In the second stage， patterned graphene was introduced as a growth template， where photolithography and plasma etching were employed to define graphene trench boundaries for guiding the oriented lateral growth of MoS₂. To regulate the interfacial chemical activity， conventional Ar/H₂ annealing was compared with a two-stage Ar/H₂ + Ar/NH₃ annealing process. Under a reduced MoO₃ dosage of 15 mg， conventional Ar/H₂ annealing tended to produce bilayer structures over different trench widths， making precise layer-number control difficult. In contrast， samples subjected to the two-stage Ar/H₂ + Ar/NH₃ annealing exhibited an increased D band intensity and decreased 2D band intensity， indicating the formation of additional defect-related active sites on the graphene surface that promoted precursor adsorption and nucleation. This mechanism effectively suppressed vertical stacking， enabling the reproducible growth of structurally uniform monolayer MoS₂ continuous films across trench widths ranging from 2 μm to 30 μm. Finally， device evaluation revealed that graphene formed extremely strong interfacial bonding with the sapphire substrate after high-temperature processing， posing significant challenges for conventional wet-transfer processes due to material damage and interlayer delamination. To avoid transfer-induced degradation， top-gate field-effect transistors (Top-gate FETs) were directly fabricated on the original sapphire substrate. This fabrication strategy establishes a feasible process for evaluating the electrical transport characteristics of graphene/MoS₂ heterostructures and provides valuable processing guidelines for future interface engineering of low-contact-resistance two-dimensional semiconductor devices.
