隨近年來資料傳輸速率不斷提升，且通道類似於低通濾波器的特性，使得資料經過通道後會受到嚴重的衰減，造成符碼間干擾(Inter Symbol Interference， ISI)以及訊號完整度的下降，導致接收端無法將資料正確判斷，並使後方電路運算錯誤以及誤碼率的上升，因此等化器被廣泛應用於接收端以補償資料經過通道所導致的衰減。 本論文所採用的等化器分別為連續時間線性等化器(Continuous time linear equalizer， CTLE)以及決策回授等化器(Decision feedback equalizer， DFE)，並使用逼零演算法結合SS-LMS的自適應系統，藉此可以分別調整CTLE和DFE的補償量。而本論文之CTLE將會針對第二級後游標ISI進行消除，等收斂達到最佳化時，將會切換成DFE迴路，而DFE則會對第一級後游標ISI進行消除，利用此方法兩種等化器既可以針對不同的通道衰減進行最佳化補償，也能降低硬體的複雜度和功耗。 本論文使用TSMC 28 nm (TN28HPCplu) 1P10M 製程實現，電路操作電壓為0.9 V，輸入之資料速率為24 Gbps，輸入時脈的頻率為12 GHz，等化器可補償通道衰減之可用範圍為14 dB到23 dB。在通道衰減為14 dB時，眼高為619.14 mV，眼寬為40.25 ps; 在通道衰減23 dB時，眼高為299.22mV，眼寬為34.68ps。在通道衰減為23 dB時，整體功率消耗為8.28 mW，其中CTLE以及DFE之等化器功率消耗為3.63 mW，自適應系統電路之功率消耗為4.65 mW，晶片面積為0.981 mm2，其中核心電路面積為0.0082 mm2。;With the continuous increase in data transmission rates in recent years， the low-pass characteristic of transmission channels severely attenuates high-frequency signals. This attenuation induces severe inter-symbol interference (ISI) and degrades signal integrity， which prevents the receiver from correctly detecting data， thereby causing operational errors in downstream circuitry and inflating the bit error rate (BER). Consequently， equalizers have been widely adopted at the receiver side to compensate for channel-induced attenuation. This thesis presents a zero-forcing-based SS-LMS adaptive architecture designed to sequentially optimize the compensation weights of the implemented Continuous-Time Linear Equalizer (CTLE) and Decision-Feedback Equalizer (DFE). The state machine orchestrates a two-stage calibration profile: the CTLE is initially deployed to suppress the second post-cursor ISI， followed by a deterministic switch to the DFE path for first post-cursor ISI eradication after the initial loop achieves steady-state convergence. This sequential multi-loop regulation accomplishes robust equalization across diverse channel attenuations without introducing hardware redundancy. The fabricated chip was implemented by TSMC 28 nm (TN28HPCplu) 1P10M CMOS process. The circuit operates at 0.9V. Operating with a 24 Gbps random data stream and a 12 GHz clock.When the channel loss is 14 dB， eye height is 619.41 mV and the eye width is 40.25 ps. When channel loss is 23 dB， eye height is 299.22 mV and the eye width is 34.68 ps. The power consumption is 8.28 mW at a supply voltage of 0.9 V and the channel loss of 23 dB. The entire equalizer and the overall adaptative system utilize 3.63 mW and 4.65 mW of power， respectively. The chip area is 0.981 mm2 and the core area is 0.0082 mm2.
