摘要 當今的計算機系統主要建構於馮紐曼架構（Von Neumann Architecture， VNA）之上，該設計的本質是將記憶體與處理器（CPU）實體拆分，兩者間的資料交換完全仰賴資料匯流排來執行。然而，伴隨人工智慧（AI）應用的快速崛起，如自然語言分析與電腦視覺等高資料密集型（Data-intensive）工作負載大幅增加。處理器必須不斷在記憶體之間頻繁搬移海量數據，衍生出嚴重的功耗與延遲問題，這也就是學界熟知的「馮紐曼瓶頸」。由於記憶體頻寬的發展遠不及運算核心的處理速度，CPU 經常處於閒置等待狀態，嚴重制約了整體系統的效能極限。 為了解決上述限制，「記憶體內運算（Computing-in-Memory， CIM）」技術成為一項關鍵突破口。該技術將運算邏輯直接內建於記憶體陣列之中，達成資料的就地（In-situ）處理，免除了資料往返傳輸的額外開銷，進而大幅強化了系統的運算吞吐量與能源效率。在本論文中，我們特別針對具備極高平行運算優勢的類比式 CIM（Analog CIM）進行探討，並選擇製程技術最為成熟的靜態隨機存取記憶體（SRAM）作為核心硬體平台。 雖然如 MRAM 或 RRAM 等新興非揮發性記憶體在儲存密度上深具潛力，但本研究最終考量到運算精準度與製程相容性，仍選定 8T-SRAM 作為開發載體。MRAM 的穿隧磁阻（TMR）比值較低，容易導致讀取訊號的區間受限；相反地，SRAM 擁有全幅（Rail-to-Rail）的電壓擺幅，可提供極佳的開關電流比（On/Off Current Ratio），這對確保類比乘加（MAC）運算的高訊號雜訊比與線性度來說不可或缺。再者，8T-SRAM 採用的讀寫路徑分離設計，能徹底解決傳統 6T 架構常見的讀取干擾（Read disturb）問題，並提供優於 RRAM 的操作壽命。基於成本、風險與效能的綜合評估，SRAM 依然是現今打造高可靠度邊緣 AI 加速器的首選。 為了進一步優化 MAC 運算效能並減少對周邊電路的依賴，本研究開發了一款 TSL-8T 運算單元。該單元導入了「混合電壓與尺寸之輸入策略」，能同時調整 SRAM 電晶體的寬長比（W/L Ratio）以及雙源極線（Shared Source Line， SSL）的脈衝振幅。此設計不僅成功抑制了傳統架構中電晶體面積隨權重位元數指數級增加的致命傷，大幅縮減了晶片面積，同時也提升了輸出電壓的線性度與系統吞吐量。實驗數據證實，與傳統的 8T-SRAM CIM 架構相比，本設計在總 CIM 陣列面積與總晶片面積上分別縮減了 21.2% 與 19.5%。而在運算效能方面，針對 4-bit x 4-bit 與 8-bit x 8-bit 的 MAC 運算，其吞吐量亦較先前文獻分別躍升了 93.7% 與 90.1%。;The foundation of contemporary computing systems relies heavily on the Von Neumann Architecture (VNA)， a model that physically isolates the central processing unit (CPU) from the memory module. In this paradigm， communication between the two components is facilitated exclusively through a data bus. However， the explosive growth of artificial intelligence applications has led to a massive increase in data-intensive workloads， including computer vision， natural language processing， and speech recognition. The constant shuttling of vast amounts of data between the memory and the processor generates significant power dissipation and transmission delays， a challenge widely recognized as the "von Neumann bottleneck". Because memory bandwidth has failed to scale at the same pace as computational core speeds， CPUs are often forced to idle while waiting for data fetches， strictly limiting overall system efficiency. Computing-in-Memory (CIM) technology offers a robust solution to bypass this performance barrier. By embedding computational capabilities directly within the memory array， CIM enables in-situ data processing. This structural shift drastically eliminates the need for data transportation， thereby significantly improving both computational throughput and system energy efficiency. Among various implementations， Analog CIM has recently drawn considerable attention due to its superior energy efficiency and massive parallel computing capacity. Consequently， this thesis centers on Analog CIM architectures， utilizing highly mature Static Random-Access Memory (SRAM) as the fundamental building block. Despite the potential of emerging non-volatile memories (NVMs) like RRAM and MRAM in terms of storage density， this study elects 8T-SRAM as the primary carrier for CIM operations. This decision is rooted in SRAM′s distinctive advantages regarding computational precision and standard process compatibility. Unlike MRAM， which is constrained by a narrow read signal window caused by a low tunneling magnetoresistance (TMR) ratio， SRAM provides a full rail-to-rail voltage swing. This property yields a tremendously high On/Off current ratio， an essential factor for preserving the signal-to-noise ratio (SNR) and high linearity during analog Multiply-Accumulate (MAC) execution. Furthermore， the decoupled read/write paths native to the 8T-SRAM architecture effectively eradicate the read-disturb vulnerabilities present in standard 6T designs while offering operational endurance that surpasses RRAM. Balancing performance， design reliability， and cost， SRAM remains the premier choice for realizing edge AI accelerators. To optimize MAC operation efficiency while mitigating peripheral circuit dependencies， this research proposes a novel SSL-8T computing macro. Utilizing a hybrid voltage-sizing input strategy， this design concurrently modulates the Width-to-Length (W/L) ratio of the SRAM transistors and the pulse amplitude of the Shared Source Line (SSL). This approach inherently prevents the exponential physical area scaling that plagues conventional designs when processing higher weight bit-counts， thus conserving significant silicon real estate. Additionally， it greatly refines output voltage linearity， thereby elevating the macro′s computational throughput. Experimental validations reveal that the proposed SSL-8T design reduces the total CIM array area by 21.2% and the total chip area by 19.5% when compared to standard 8T-SRAM CIMs. Moreover， it achieves remarkable throughput enhancements of 93.7% and 90.1% for 4-bit x 4-bit and 8-bit x 8-bit MAC operations， respectively， outperforming prior implementations.
