自旋轉移矩磁阻式隨機存取記憶體(STT-MRAM)能夠因應傳統記憶體在製程微縮所面臨的挑戰，因此被視為新興記憶體的候選技術。然而，STT-MRAM具有較小的高低電阻比，且容易受到溫度變異的影響，導致其讀取可靠度低。為了改善此問題，STT-MRAM通常採用可修整的參考電阻架構，使得晶片在製造後可以透過調整參考電阻與感測放大器來提升讀取可靠度。現有的修整架構可以分為參考修整與資料修整；其中，參考修整又可以進一步分為全域參考電阻修整架構與合併式參考位線修整架構。 本論文針對不同STT-MRAM修整架構提出高效率的修整測試方法。首先，針對全域參考電阻修整架構，提出平行檢查修整測試(PCTT)方法與局部二元搜尋(LBS)修整測試方法，分別用於決定全域與局部修整碼。其中，PCTT方法可將修整測試時間最多縮短41.67%，並達到最高92.31%的Proximity(接近理想參考電阻的程度)，相較於現有的全域二元搜尋(GBS)修整測試方法的91.48%更佳。此外，LBS 修整測試方法的 Proximity 平均值最高可達 90.9%，亦高於現有 GBS 修整測試方法的平均值 87%。 此外，針對採用局部參考電阻架構之合併式參考位線修整架構，本論文提出兩階段區間修整測試(TSIT)方法，以有效選擇製造後的最佳比例之修整碼。在修整前，先利用交錯式參考位線選擇方法固定參考電阻值，再執行TSIT修整測試。實驗結果顯示，所提出的TSIT方法可以將測試複雜度最多降低至46%，同時達到最高96.52%的Proximity。最後，本論文進一步將PCTT和LBS修整方法延伸至資料修整架構，透過調整資料單元的有效電阻進行修整。 另外，本論文建立了一套完整的模擬分析架構，以定量評估不同修整架構與修整測試方法的效能。分析結果比較了各種架構在 Proximity 與讀取餘裕上的表現，並探討讀取可靠度與測試複雜度之間的取捨關係。結果顯示，合併式參考位線修整架構相較於其他修整架構具有較佳的 Proximity 與讀取餘裕。本論文亦透過考慮製程與溫度變異的蒙地卡羅模擬驗證所提出的修整測試方法之效能。實驗結果證明，相較於現有方法，所提出之修整測試方法能在降低測試複雜度的同時提升讀取可靠度，因此適用於 STT-MRAM 的設計。其中，在適用於合併式參考位線修整架構的各項方法中，TSIT 能在維持與其他方法相當修整精度的同時，大幅縮短修整測試時間。 為支援設計自動化，本論文亦開發一套以 Python 為基礎的編譯器，可自動產生所提出修整測試方法的 Verilog RTL。藉由自動化產生複雜的控制流程與修整邏輯，此設計流程可大幅降低設計工作量。由於編譯器採用參數化設計，可支援不同記憶體規格，因此能快速整合至既有 STT-MRAM 測試架構中。;Spin-transfer-torque magnetic random access memory (STT-MRAM) is a candidate for next-generation memory to cope with scaling challenges of conventional memories. However， the STT-MRAM has a small on/off resistance ratio and susceptibility to thermal variations which leads to low read reliability. To address these issues， STT-MRAMs typically adopt trimmable reference resistance schemes， enabling post-production calibration of the reference resistance and sense amplifier (SA) to enhance read reliability. Existing trimming schemes can be broadly classified into reference trimming and data trimming schemes. Furthermore， reference resistance trimming schemes can be categorized into global reference resistance and merged reference bitline trimming schemes.
In this thesis， we propose efficient trimming test approaches for various STT-MRAM trimming schemes. First， for the global reference resistance trimming scheme， a parallel-check trimming test (PCTT) approach and a local binary search (LBS) trimming test approach are proposed to determine global and local trim codes， respectively. The PCTT approach significantly reduces the trimming test time of up to 41.67% and a higherProximity (close to the ideal reference resistance) of up to 92.31%， compared to 91.48% for the existing global binary search (GBS) trimming test approach. The LBS trimming test approach achieves a higher Proximity of up to a mean value of 90.9% compared to a mean value of 87% for the existing GBS trimming test approach.
Furthermore， for the merged reference bitline trimming scheme implemented with a local reference resistance scheme， a two-step interval trimming (TSIT) test approach is proposed to efficiently select an appropriate ratio (trim code) after manufacturing. Prior to trimming， an interleaving reference bitline selection method is used to fix the reference resistance values first. The proposed TSIT test approach significantly reduces test complexity of up to 46% while achieving a Proximity of up to 96.52%. Lastly， the PCTT and LBS trimming test approaches are further extended to support the data trimming scheme， where the effective resistance of the data cells can be tuned.
In addition， a comprehensive simulation framework is developed to quantitatively evaluate different trimming schemes and trimming test approaches. The analysis compares the Proximity and RM across various configurations， highlighting the trade-offs among read reliability and test complexity. The merged reference bitline scheme is shown to provide better Proximity and RM compared to the other trimming schemes. Furthermore， the effectiveness of the proposed trimming test approaches is evaluated through Monte Carlo simulations under process and temperature variations. Experimental results demonstrate that the proposed trimming test approaches improve read reliability while reducing test complexity compared to existing methods， making them suitable for STT-MRAM designs. Among the proposed approaches applicable for the merged reference bitline scheme， TSIT achieves trimming accuracy comparable to the other approaches while significantly reducing the trimming test time.
To support design automation， a Python-based compiler with automated Verilog RTL generation of the proposed trimming test approaches is also developed. By automating the generation of complex control flows and trimming logic， the proposed framework significantly reduces design effort. Furthermore， the parameterized nature of the compiler enables scalability to various memory configurations， facilitating rapid integration into existing STT-MRAM test architectures.
