近年來，大型語言模型(Large Language Model， LLM)已成為代理人式人工智慧系統的核心，並逐漸朝邊緣與個人化裝置部署，以兼顧反應速度、資料隱私與客製化需求。在運算與記憶體資源受限的邊緣裝置上，參數高效微調(Parameter-Efficient Fine-Tuning， PEFT)成為可行之微調途徑，其中又以低秩適配(Low-Rank Adaptation， LoRA)最具代表性。然而固定的內在秩難以同時適應難易不一的任務。既有的動態秩調整方法(如 AdaLoRA、SoRA 與 SalientLoRA)雖能依任務調整秩，卻皆仰賴秩剪枝機制，為涵蓋多樣任務必須預先設定較高的初始秩，對晶片內記憶體(on-chip SRAM)造成沉重負擔，限制其於邊緣加速器上的可行性。本論文首先針對含門控單元之 Sparse LoRA 反向傳播進行梯度推導，並以分塊串流之資料流排程分析其晶片內 SRAM 需求，定量指出初始秩之設定為邊緣加速器設計之關鍵瓶頸。據此，本論文提出可擴展稀疏低秩適配(Scalably Sparse LoRA， SSLoRA)演算法，將秩剪枝與秩增強兩種相反策略整合於回合式(episodic)訓練流程：以較小的初始秩出發，於回合內透過近端梯度下降之軟閾值剪枝以利用稀疏性，並於回合之間以效能感知之條件式合併與自適應正規化強度排程器決定是否增強秩，兼顧稀疏性與可擴展性。於編碼器架構(DeBERTaV3)之 GLUE 基準與解碼器架構(TinyLlama)之問答任務上，SSLoRA 均能以較低之保留參數比例，達到與 SoRA 相當甚至更佳之效能。在硬體層面，本論文以一既有之混合精度 LoRA 訓練加速器為基礎，在不重建矩陣乘法陣列且不破壞既有 AdamW 權重更新路徑之前提下，以最小硬體增量擴充對含門控向量之 Sparse LoRA 反向傳播之支援，新增門控暫存器、指令解碼與向量單元之門控縮放及合併相加的歸約路徑，完成門控相關之新增運算，並透過位元精確之硬體行為模擬驗證其正確性，同時確認既有 LoRA 權重更新功能不受影響。整體結果顯示，SSLoRA 為一兼具演算法效能與硬體效率之邊緣端微調解決方案。;Large language models have become the backbone of modern AI systems， and are increasingly deployed on edge and personal devices to meet the demands for responsiveness， data privacy， and personalization. Under the stringent computation and memory constraints of edge devices， parameter-efficient fine-tuning (PEFT) has emerged as a practical fine-tuning approach， among which low-rank adaptation (LoRA) is widely adopted. However， a fixed intrinsic rank is often suboptimal across tasks of varying difficulty. Existing dynamic rank-adjustment methods can adapt the rank per task but all rely on rank pruning， which requires a relatively large initial rank. This imposes a heavy burden on on-chip SRAM， limiting their feasibility on edge devices. This thesis first derives the back-propagation gradients of the gated Sparse LoRA， and analyzes its on-chip SRAM requirement under a tiled streaming dataflow， quantitatively showing that the initial rank setting is a bottleneck for edge accelerator design. A scalably sparse LoRA (SSLoRA) algorithm is then proposed， which integrates the two opposite strategies of rank pruning and rank augmentation within an episodic training procedure. Experiments on the GLUE benchmark with an encoder-based backbone and on question-answering tasks with a decoder-based backbone (TinyLlama) show that SSLoRA achieves performance comparable to or better than SoRA while retaining fewer parameters. At the hardware level， this thesis extends an existing mixed-precision LoRA accelerator with minimal hardware overhead to support the back propagation of the gated Sparse LoRA. Gate registers， instruction decoding， and the gate-scaling as well as inner product datapaths in the vector unit are designed to realize the two newly required gate-related operations. The results demonstrate that SSLoRA is a performance- and hardware-efficient solution for fine-tuning on edge devices.
