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    請使用永久網址來引用或連結此文件: https://ir.lib.ncu.edu.tw/handle/987654321/111217


    題名: 三相並聯Vienna整流器考慮輸出電壓不平衡之輸入電流零交越失真補償之研製;Development and Implementation of Paralleled Three-Phase Vienna Rectifiers with Input Current Zero-Crossing Distortion Compensation under Unbalanced Output Voltage
    作者: 葉昕;YE, SIN
    貢獻者: 電機工程學系
    關鍵詞: Vienna 整流器;Vienna交錯並聯拓樸;不連續脈衝寬度調變;輸出電壓不平衡控制;零交越失真;Vienna Rectifier;Interleaved Parallel Vienna Topology;Discontinuous Pulse Width Modulation (DPWM);Unbalanced Output Voltage Control;Zero-Crossing Distortion
    日期: 2026-08-29
    上傳時間: 2026-10-20 17:04:44 (UTC+8)
    出版者: 國立中央大學
    摘要: 單台 Vienna 整流器在本質上屬於非雙向功率潮流之電路拓樸,受限於電網側電流流經前端升壓電感所引發之感抗壓降,極易導致輸入電流極性與極電壓發生不匹配,進而使輸入電流於零交越點產生波形失真。隨著工業界對高輸出功率轉換器之需求日益殷切,單台 Vienna 整流器之架構已不足以應付高負載產業應用,因而促使交錯並聯型拓樸逐漸成為主流。然而,縱使系統操作於並聯型 Vienna 整流器架構下,電流零交越失真問題依舊無法完全規避;若進一步導入直流側上下臂電壓主動不平衡控制,更將導致零交越區間輸入電流與極電壓之極性不匹配現象愈發嚴重,甚至反向引發輸出側直流電壓於零交越點附近產生劇烈擾動。有鑑於此,本文提出一種兼顧電網側輸入電流與直流側輸出電壓的控制策略。該策略在無需頻繁調節載波移相角度的前提下,能有效抑制輸入電流的零交越失真,並降低直流輸出電壓的擾動,從而確保系統具備良好的交流側電流品質與直流側穩態響應。最後,本文建置一台 2.5 kW 之並聯型三相 Vienna 整流器實驗平台進行實機驗證,並詳實對比傳統不連續脈衝寬度調變(Discontinuous Pulse Width Modulation, DPWM)技術與所提策略於輸出主動不平衡情況下之輸入電流總諧波失真(THD)與直流側電壓品質。;A Vienna rectifier inherently exhibits a unidirectional circuit topology. Due to the in-ductive voltage drop induced by the grid-side current flowing through the front-end boost inductor, a polarity mismatch between the input current and the pole voltage easily occurs, thereby yielding current waveform distortion at the zero-crossing points. With the growing industrial demand for high output power rating, the standalone Vienna rectifier architecture has become insufficient for high-load industrial applications, thereby driving the interleaved parallel topology to gradually become mainstream. Nevertheless, even when the system op-erates under the parallel Vienna rectifier architecture, the issue of current zero-crossing dis-tortion remains inevitable. If active unbalance control for the DC-link top and bottom ca-pacitor voltages is further introduced, the polarity mismatch within the zero-crossing region is further aggravated, which can even conversely induce severe fluctuations in the output DC voltage near the input current zero-crossing points.
    To address these challenges, this paper proposes a control strategy that simultaneously suppresses the grid-side input current zero-crossing distortion and mitigates the DC output voltage oscillation without requiring frequent adjustments to the carrier phase-shift angle, thereby eliminating AC-side input current zero-crossing distortion and ensuring a stable DC-side output voltage steady-state performance. Finally, a 2.5 kW parallel three-phase Vi-enna rectifier experimental platform is established for hardware verification. The input cur-rent total harmonic distortion (THD) and the DC-link voltage quality are comprehensively compared between the conventional discontinuous pulse width modulation (DPWM) tech-nique and the proposed strategy under active unbalanced output voltage conditions.
    顯示於類別:[電機工程研究所] 博碩士論文

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