自旋轉移力矩磁性隨機存取記憶體（Spin-Transfer Torque Magnetic Random Access Memory， STT-MRAM）具有高速、低功耗、高耐久度以及非揮發性等優點，因此被視為極具潛力的次世代記憶體技術。然而，製程變異會造成STT-MRAM 記憶體單元的電阻分布發生偏移，進而降低感測裕度（sensing margin），並導致讀取錯誤以及良率下降。因此，有效的修整（trimming）與修復（repair）技術對於提升STT-MRAM 的可靠度與良率而言相當重要。
本論文第二部分針對製程變異可能造成部分記憶體單元成為離群單元（outlier），進而導致讀取錯誤的問題進行研究。為提升修復資源的使用效率，本論文提出一種故障辨識演算法（fault distinguishing algorithm），將測試過程中偵測到的故障區分為硬故障（hard fault）、軟故障（soft fault）以及離群單元（outlier），並根據不同的故障類型選擇適合的修復資源。其中，離群單元可透過調整修整碼（Trim Code， TC）進行修復，而硬故障則利用冗餘資源（redundancy）進行修復。此外，本論文提出一種內建冗餘分析Built-In Redundancy Analysis， BIRA）方法，以支援冗餘資源與修整碼的配置，並進一步設計採用所提出BIRA 方法的內建自我修復（Built-In Self-Repair，BISR）架構。模擬結果顯示，所提出的BISR 架構在約7% 的面積額外成本下，可提升約0.5%–3.5% 的修復後良率。;Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) has the features of high speed， low power consumption， high endurance， and non-volatility. Therefore， it is regarded as a promising next-generation memory technology. However， process variation causes the resistance distribution of STT-MRAM cells to shift， thereby degrading the sensing margin and resulting in read failures and yield loss. Effective trimming and repair techniques are essential for improving the reliability and yield of STT-MRAMs. In the first part of this thesis， a Watermark-Based Trimming (WMT) method is proposed to reduce the test time of reference trimming. The WMT method starts from the highest reference resistance and progressively searches downward to identify a suitable boundary. When the reference resistance is adjusted， the method reuses the previously verified boundary information instead of retesting the entire memory array from the beginning， thereby reducing redundant read operations and shortening the overall test time. Simulation results demonstrate that， compared with previous trimming techniques， the proposed WMT method reduces the test time by approximately 23.38%–63.11%. In the second part of this thesis， process variations may cause some memory cells to become outliers， resulting in read failures. To optimize the repair repair efficiency， a fault distinguishing algorithm is proposed to classify detected faults as hard faults， soft faults， or outliers. Then different repair resources are selected to repair the cells with different fault types. Outlier cells are repaired by adjusting the trim code(TC). In contrast， hard faults are repaired by redundancy. A built-in redundancy analysis (BIRA) approach support the redundancy and TC allocation is proposed. A built-in self-repair scheme using the proposed BIRA approach is designed as well. Simulation results show that BISR scheme improves the repaired yield by approximately 0.5%–3.5% with an area overhead of approximately 7%.
