本論文採用 WIN 100-nm GaAs pHEMT PP10-20 製程，實現操 作於 Q 頻段與 W 頻段之單級功率放大器。 第二章設計一組操作於 Q 頻段（40 GHz）之單級功率放大器， 使用 WIN 100-nm GaAs pHEMT PP10-20 製程。為了提升模擬與量 測的一致性，本電路參考先前下線電路量測結果，並在重新設計時考 慮寄生效應，加入寄生元件模型進行電路優化。為了有效縮減晶片整 體面積，電路匹配採用並聯傳輸線與串聯電容進行匹配。量測結果顯 示，在 40 GHz 下具備 7.2 dB 增益，OP1dB 為 20.1 dBm，於 OP1dB 時的功率附加效率（PAE）為 27.4%。 第三章則延伸此製程之更高頻段進行設計，實現操作於W 頻段 （94 GHz）之單級功率放大器。電路設計上以傳輸線架構完成輸入與 輸出匹配。量測結果顯示，在 94 GHz 下增益約 6.3 dB， OP1dB 為 14.6 dBm，PAE 達 15.9%。;This thesis presents the design and implementation of single-stage power amplfiers operating in the Q-band and W -band using the WIN 100-nm GaAs pHEMT PP10-20 process. In Chapter 2， a single-stage power amplfier operating in the Qband (40 GHz) is designed using the WIN 100-nm GaAs pHEMT PP10- 20 process. To improve the consistency between simulation and measurement， this circuit refers to the measurement results of a previously fabricated circuit， considers parasitic eects during redesign， and incorporates parasitic component models for circuit optimization. In order to eectively reduce the overall chip area， the circuit matching adopts shunt transmission lines and series capacitors. The measurement results show that it achieves a gain of 7.2 dB at 40 GHz， an OP1dB of 20.1 dBm， and a power-added eciency (PAE) of 27.4% at OP1dB. Chapter 3 extends the design to a higher frequency band of this process， realizing a single-stage power amplfier operating in the W -band (94 GHz). The circuit matching is accomplished using transmission-line structures for both input and output matching networks. The measurement results show that it achieves a gain of approximately 6.3 dB at 94 GHz， an OP1dB of 14.6 dBm， and a PAE of 15.9%
