基於小晶片的積體電路（chiplet-based ICs）透過先進封裝技術整合多個小晶片（chiplet）。此整合技術可使各小晶片採用最適合的製程技術進行製造，進而最佳化整體效能與成本。此外，單一小晶片較小的尺寸亦有助於提升製造良率。小晶片之間的通訊可透過高速晶片間互連介面（die-to-die interconnect interface）實現，例如通用小晶片互連標準（Universal Chiplet Interconnect Express， UCIe）。 為提升良率，晶片間互連介面通常配置冗餘資源（redundancy）。這隱含了配對具有錯誤I/O的晶片（die）以提升晶片對之良率的可能性。然而，在接合前測試（pre-bond test）階段，高速 I/O 通常採用迴授路徑測試（loopback test）進行測試，卻會增加錯誤定位（fault localization）的困難度。在本論文的第一部分中，我們提出一種適用於接合前測試階段、基於迴授路徑測試的高速 I/O 錯誤定位方法。此外，亦設計一套內建自我測試（built-in self-test， BIST）以實現所提出的錯誤定位方法，並可根據表徵（syndrome）分析結果輸出其可修復性（repairability）。分析結果顯示，所提出的錯誤定位方法可達到 99.9% 的錯誤定位準確率。 在接合後（post-bond）階段，高速晶片間互連介面的訓練通常使用偽隨機二進位序列（pseudo-random binary sequence， PRBS）執行。因此，在本論文的第二部分中，我們提出一種特徵多項式配置方法，以產生可涵蓋晶片間互連串擾錯誤（crosstalk faults）的 PRBS 圖樣，並應用於接合後測試（post-bond test）階段。此外，本論文亦提出一套內建自我修復（built-in self-repair， BISR）機制，利用冗餘資源與驅動能力調整（driving capability adjustment），修復眼圖寬度劣化（eye-width degradation）的晶片間互連。相較於僅使用冗餘資源的傳統方法，在不同互連變異條件下，所提出的 BISR 機制可使修復率提升 3.2% 至 30.4%。;Chiplet-based ICs integrate multiple chiplets using advanced packaging technology. This integration technology allows each chiplet to be fabricated using the most suitable process technology， thereby optimizing overall performance and cost. In addition， the smaller size of individual chiplets contributes to improved manufacturing yield. Communication between chiplets can be realized through high-speed inter-die interconnect interfaces， such as Universal Chiplet Interconnect Express (UCIe). To enhance the yield， inter-die interconnect interfaces typically include redundancies. This implies the possibility of matching dies with defective I/Os to improve the yield of a pair of dies. In the pre-bond test phase， however， the loopback test approach is often used to test the high-speed I/Os， which causes difficulty in fault-localization. In the first part of this thesis， we propose a fault-localization method for high-speed I/Os in the pre-bond test phase using the loopback test approach. A built-in self-test (BIST) is also designed to realize the fault-localization approach， which can export the repairability according to the syndrome analysis. Analysis results show that the proposed fault-localization approach can achieve 99.9% fault-localization accuracy. In the post-bond phase， the pseudo random binary sequence (PRBS) is used to execute the training of high-speed inter-die interconnect interfaces. In the second part of this thesis， therefore， we propose a characteristic polynomial assignment approach to generate PRBS patterns to cover crosstalk faults of inter-die interconnects in the post-bond test phase. In addition， a built-in self-repair (BISR) scheme is proposed to repair the eye-width-degraded inter-die interconnects by using redundancy and driving capability adjustment. Compared with the traditional approach using redundancy only， the proposed BISR scheme can achieve 3.2% to 30.4% repair rate increment with respect to different variation conditions of interconnects.
