自旋轉移力矩磁性隨機存取記憶體（spin-transfer-torque magnetic randomaccess memory， STT-MRAM）是具潛力的嵌入式非揮發性記憶體技術。然而機率性轉態造成寫入可靠度的挑戰，因此需要有效的寫入修剪技術以滿足預期寫入失誤率（write error rate， WER）。 本論文第一部分提出一種以外插法為基礎的寫入修剪預測（extrapolation-based prediction write-trimming， EPWT）方法用於選擇可滿足預期WER 的寫入電壓或寫入時間。傳統線性修剪搜尋需要大量取樣才能量測低WER 區域中各個寫入條件所對應的WER，相較之下EPWT 方法使用較少的樣本量測10−3--10−5 範圍的WER，並透過外插選擇低於10−6 預期WER 的寫入條件。相比於線性修剪搜尋，在10 ns 的修剪解析度及不同製程變異程度下EPWT 方法可將測試時間降低約67.7%--69.3%，同時使平均WER維持接近於預期WER 10−6 ，並寫入能量降低0.51%--3.07%。 另一方面，驗證後重寫（write-verify-write， WVW）策略可用於判斷寫入操作是否成功。然而使用讀取參考電阻進行驗證時，可能會將陷入中間狀態intermediate state， IM state）記憶體單元判定為寫入成功。IM state 的電阻可能在未施加寫入操作的情況下，隨後復原至平行（parallel， P）或反平行（antiparallel， AP）狀態。若記憶體單元復原至與預期寫入值相反的狀態，儲存位元將發生軟錯誤(soft error)。本論文第二部分提出一種用於驗證之自適應參考電阻的IM state 篩選方法。在生產測試期間，參考電阻修剪機制根據製程變異下觀察到的IM state 電阻分布，調整低、高參考電阻（RL 與 RH）。在WVW 驗證期間，系統根據預期寫入值選擇對應的參考電阻，使IM state 記憶體單元能被辨識為寫入失敗並重新寫入，直到其不再停留於IMstate。相較於使用讀取參考電阻進行驗證，此方法在1% 與5% 製程變異下，平均軟錯誤率（soft error rate， SER）分別降低81.26% 與39.98%。 最後，本論文針對STT-MRAM 設計一套可程式化內建自我測試（programmable built-in self-test， PBIST）電路架構，以支援March 測試、讀寫修剪與診斷。 此PBIST 採用22 nm ULL CMOS 技術，並以時序100 MHz 的MRAM 進行設計。March測試模組的面積為5，668 μm2，寫入修剪模組的面積則為2，480.44 μm2。;Spin-transfer-torque magnetic random-access memory (STT-MRAM) is a promising nonvolatile memory technology for embedded applications， but its inherent stochastic switching behavior presents write-reliability challenges. Effective write-trimming techniques are therefore essential for satisfying the target write error rate (WER). In the first part of this thesis， an extrapolation-based prediction write-trimming (EPWT) method is proposed to select an appropriate write voltage and/or write time that satisfies the target WER. Instead of using a linear trimming search that requires extensive sampling to measure the WER at each write setting in the low-WER region， the EPWT method measures WERs in the 10−3–10−5 range using fewer samples and extrapolates these measurements to select a write setting for a target WER below 10−6. Compared with linear trimming search， the EPWT method reduces the test time by approximately 67.7%–69.3% while maintaining the final WER near the target of 10−6 under different levels of process variation with a 10 ns trimming resolution. The normalized write energy is also reduced by 0.51%–3.07% at this resolution. On the other hand， a write-verify-write (WVW) strategy can be used to determine whether a write operation has completed successfully. However， verification using a conventional read reference may identify an intermediate (IM) state cell as a successful write. The IM state resistance may subsequently relax to either the P or AP state without an additional write operation. If the cell relaxes to the state opposite to the intended written value， the stored bit becomes incorrect and causes a soft error. In the second part of this thesis， an adaptive verify-reference IM state screening method is proposed. During production testing， a reference-trimming scheme adjusts the low and high reference resistances (RL and RH) according to the observed IM state resistance distribution under process variation. During WVW verification， the appropriate reference is selected according to the intended written value， allowing IM state cells to be identified as write failures and rewritten until they no longer remain in the IM state. Relative to verification using a conventional read reference， the method achieves mean SER reductions of 81.26% at 1% process variation and 39.98% at 5% process variation. Finally， a programmable built-in self-test (PBIST) scheme is developed for STT-MRAM to support March tests， read and write trimming， and diagnosis. The PBIST is designed using 22 nm ultra-low-leakage (ULL) CMOS technology under a 100 MHz MRAM timing constraint. The March test module occupies 5，668 μm2， whereas the write trimming module occupies 2，480.44 μm2
