大型語言模型在邊緣運算裝置上進行微調的挑戰包含外部記憶體資料搬移、低秩矩陣的不規則形狀，以及多精度訓練運算的硬體成本。本論文提出一套由 RISC-V 自訂指令控制、運用於低秩適配（Low-Rank Adaptation， LoRA）微調的混合精度加速器。首先將 LoRA 前向傳遞、反向傳遞與 AdamW 權重更新拆解為張量運算與個別元素運算，再透過矩陣分割、資料保留及晶片內部分和累加等技術降低中間資料搬移的能耗。混合精度核心透過共享的部分乘積產生器、多功能乘加單元（multi-function multiply-accumulate， MFMAC）與管線化區塊浮點數路徑來支援整數乘整數、浮點數乘整數及浮點數乘浮點數等運算。共享 MFMAC 核心相較於各模式獨立運作的乘法器可減少 24.8% 的面積。針對 LoRA 梯度的瘦高與寬扁矩陣，能耗模型在指定工作負載、緩衝容量與係數下選得 6.95 mJ 的動態分割排程，較其他三種傳統固定分割處理資料流降低 16.1% 至 59.1% 的能耗。系統架構整合全域緩衝區、四個張量單元、向量單元及自訂指令控制，以執行 LoRA 矩陣運算與 AdamW 更新。位元精確驗證中，張量單元的輸出與向量單元的輸出皆與軟體黃金模型逐位元一致。於固定模型、資料與單次訓練設定下，位元精確模型與 PyTorch LoRA 對照驗證，在 BoolQ 的正確率分別為 80.5810% 與 80.6422%，在 WinoGrande XL 分別為 73.88% 與 73.80%，XSum 的 ROUGE-L 則皆為 0.2919，未觀察到明顯的任務品質下降。硬體張量單元排程的週期利用率為 99.14% 至 100%；28 nm 前佈局合成與功耗估計顯示，設計在 400 MHz 下的面積為 3.1082 mm²，理論峰值吞吐量為 0.8192 TFLOPS，低秩梯度鏈與梯度回傳鏈的能源效率為 1.52 與 1.34 TFLOPS/W。上述結果顯示，所提出方法經位元精確驗證，具備以 LoRA 硬體加速器在邊緣運算裝置進行微調的可行性。 關鍵詞：低秩適配、混合精度、張量加速器、能耗感知資料流、RISC-V 自訂指令、位元精確驗證;Low-rank adaptation (LoRA) of large language models on edge devices is constrained by external memory access， the irregular shapes of low-rank matrices， and the implementation cost of mixed-precision training. This thesis presents a mixed-precision accelerator controlled by RISC-V custom instructions for LoRA fine-tuning. The LoRA backward pass and AdamW update are decomposed into tensor and element-wise operations， while design strategies for matrix tiling， data retention， and on-chip partial-sum accumulation are proposed to reduce energy consumption. The shared multi-function multiply-accumulate (MFMAC) core supports integer-by-integer， floating-point (FP)-by-integer， and FP-by-FP operations， and achieves 24.8% less area than separately inferred multipliers. For the tall-and-skinny and wide-and-short matrices in LoRA gradients， the dynamic tiling schedule reduces energy consumption by 16.1%–59.1% compared with the three conventional fixed-tiling schemes. The system integrates a global buffer， four tensor units， a vector unit， and custom-instruction control to execute LoRA matrix operations and AdamW updates. All tensor-unit and vector-unit outputs match the software golden model bit for bit. The bit-true model differs from the PyTorch LoRA model by less than 1% on BoolQ and WinoGrande XL， and both obtain a ROUGE-L score of 0.2919 on XSum. The tensor units reach 99.14% to 100% cycle utilization for LoRA back propagation. Pre-layout synthesis and power estimation in a 28-nm process report an area of 3.1082 mm² at 400 MHz， a theoretical peak throughput of 0.8192 TFLOPS， and energy efficiencies of 1.52 and 1.34 TFLOPS/W for the LoRA parameter-gradient and gradient propagation workloads， respectively. These results show the feasibility of fine-tuning on edge devices.
