| 摘要: | 近年來在新穎奈米元件研發中，能將0 維及1 維奈米材料直接整合於矽基半導體基材上之先進製程技術逐漸受到廣泛的研究。在實際矽晶奈米元件應用上，釐清不同維度奈米材料與矽基晶片間之界面反應及其對應的特性變化常是決定這些奈米結構材料能否真正整合應用於未來先進半導體元件上最關鍵性的部分。然而，目前針對探討金屬奈米材料與矽基半導體基材間之界面反應機制與結構變化的相關研究仍十分缺乏。此外，規則序化排列的奈米結構在先進光電元件、生物感測器及資料儲存上都有很大的應用潛力。但要如何控制製備大面積規則排列且尺寸均勻之奈米結構卻一直是相關製程急需克服的重大挑戰。因此，本計畫之主要研究目標將由研發新穎之自組裝模板法製程技術著手，以嘗試直接在不同半導體晶片上皆能控制成長規則排列且尺寸可調變之0 維及1 維新穎奈米結構陣列，並藉助具高解析度分析儀器有系統地探討並釐清其與各式半導體基材間界面反應動力學、相變化機制，以及不同奈米結構材料陣列在不同半導體晶片上之電性、磁性、場發射等特性表現。本計畫擬以二年為期，除需逐步添購實驗必須之設備外，在相關實驗執行規劃上將由研發一系列新穎奈米模板製程技術著手，並嘗試將其直接整合於矽基半導體晶片上，再針對以下四個子題分年分階段進行深入研究：一、 新穎自組裝奈米模板之製程研發及其整合於矽基半導體晶片上之研究。二、 矽基半導體晶片上以新穎奈米模板操控成長不同維度規則金屬奈米結構陣列及其性質研究。三、 不同維度、尺度之金屬/半導體奈米異質界面反應機制研究。四、 掌握製備有序排列0 維及1 維優質金屬矽化物奈米陣列之最佳製程條件及其電、磁、場發射特性研究。 Recently, for the development of novel nanoscale devices, the advanced process technologies for the direct integration of 0-D and 1-D nanomaterials into Si-based semiconductor substrates have attracted much attention. For the applications of Si nanodevices, in-depth understanding the interfacial reactions between the nanomaterials and Si-based substrates will play a key role in defining the use of these nanomaterials in advanced nanodevices. However, the studies on the silicidation reactions and microstructure transitions of these metal nanomaterials on Si-based substrates after different heat treatments are extremely rare. On the other hand, well-ordered nanostructures have already been found their potential applications in advanced optoelectronic devices, biosensors, and data storage. However, the size uniformity and periodicity are the major challenges in the fabrication of nanomaterials. Therefore, in this project, particular emphasis will be focused on the development of novel self-assembly template approaches, synthesis of well-ordered, size-tunable novel 0-D and 1-D nanostructure arrays on various Si-based substrates, and systematically investigating the growth kinetics, phase transition mechanisms, and the electrical, magnetic, and field-emission properties of the formed nanomaterials. The objectives for the two-year project are to develop the novel template techniques and to integrate these techniques into the Si-based substrates to allow the nanostructures to be formed controllably and devices to be fabricated. The main tasks include： 1. Development of novel template techniques and integration of these novel template techniques on the Si-based substrates. 2. Nanotemplate-controlled fabrication of well-ordered metal nanostructured arrays on the Si-based substrates and their properties characterization. 3. Interfacial reactions of metal nanomaterial arrays on Si-based semiconductor substrates. 4. To establish the optimum process conditions for fabrication of high-quality, well-ordered 0-D and 1-D metal silicide nanostructure arrays and their properties characterization. 研究期間 : 9808 ~ 9907 |
