本論文提出一寬範圍電壓操作之超低功率全數位式鎖相迴路，不僅擁有低功率上的優點，並且在電源操作電壓上可從1.8 V 提升至3.6 V 的寬範圍設計，使用新型責任週期校正器電路獲得責任週期50%，並提出以環型振盪器和除頻器組合的數位控制振盪器之電路設計，使其可操作在寬範圍操作電壓。全數位式鎖相迴路晶片之製作以TSMC 0.35 um 2P4M 製程實現晶片，當操作電壓為1.8 V 時，其操作頻率範圍為1.5 MHz ~ 11.44 MHz，而操作電壓為3.6 V 時，其操作頻率範圍為1.5 MHz ~ 11.44 MHz，並且鎖定時間在23 個輸入週期內鎖定。整體晶片的面積為680 x 680 um2，核心電路的面積為383 x 368 um2 ，而新型責任週期校正器電路之責任週期在輸出頻率為8.38 MHz 時更可達50±0.8%，其輸出訊號之最大抖動量(P2P Jitter)的百分比為3% (操作電壓為1.8 V 為3.7 ns 而操作電壓為3.6 V 為3.6 ns)，並且可應用於數位電子式水表中之微處理器裡。在電流消耗部份操作電壓為1.8 V 時更只有36 uA，其功率消耗在操作電壓為1.8 V僅有64 uW 而在操作電壓為3.6 V 下也僅有234 uW。 In this work, an ultra low power all digital phase locked loop(ADPLL) has wide power supply voltage range from 1.8 V to 3.6 V. ADPLL uses the proposed duty cycle corrector for 50% duty cycle. The ring oscillator and divider are used for digital controlled oscillator(DCO). Thus, DCO can operate wide power supply voltage range. ADPLL is implemented by TSMC 0.35 um 2P4M process. The output frequency range is 1.5 MHz ~ 11.44 MHz at 1.8 V, and output frequency range is 4.5 MHz ~ 24.49 MHz at 3.6 V. The locking time of ADPLL is less than 23 reference clock cycles. The chip area and core area are 680 x 680 um2 and 383 x 368 um2, respectively. The proposed duty cycle corrector is 50±0.8% at 8.38 MHz. The peak-to-peak jitter of ADPLL is 3% at 8.38 MHz for digital water meter application of microcontroller(3.7 ns at 1.8 V and 3.6 ns at 3.6 V). The operating supply current is less than 36 uA at 1.8 V, and power consumption is 64 uW at 1.8 V and 234 uW at 3.6 V.
