應用於SATA-III之6 Gbps半速率時脈與資料回復電路 ; Design and Implementation of 6 Gbps Half-Rate Clock and Data Recovery Circuit for SATA-III Application

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/25801

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/25801

Title:	應用於SATA-III之6 Gbps半速率時脈與資料回復電路;Design and Implementation of 6 Gbps Half-Rate Clock and Data Recovery Circuit for SATA-III Application
Authors:	陳炳宏;Bing-hung Chen
Contributors:	電機工程研究所
Keywords:	混和訊號;鎖相迴路;時脈與資料回復電路;mixed-signal;phase lock loop;clock and data recovery
Date:	2009-10-19
Issue Date:	2010-06-11 16:20:16 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	由於近年來製程演進使得處理器及記憶體等運算單元及儲存元件之間的溝通量越來越大，傳統匯流排已不敷使用，因此高頻寬之收發器逐漸成為下一世代主流。高速傳輸技術的應用從光纖通訊發展到電腦通用I/O介面，經由電纜或匯流排作為傳輸媒介的高速串列介面。本論文之設計主要針對串列有線傳輸系統中的Serial-ATA III接收端規格為設計藍圖，採用雙迴路相位選擇式架構，利用半速率取樣方式實現時脈與資料回復電路。本論文所設計實現的時脈與資料回復電路應用於6 Gbps的串列傳輸系統，輸出為二組3 Gbps並列資料。其中雙迴路相位選擇式架構分別由多相位時脈倍頻器與資料回復迴路所組成。其主要優勢在於二個獨立迴路，可以解決單一迴路中抖動轉移函數與抖動容忍度的頻寬互相衝突的問題。在資料回復迴路中，利用改良後的資料延遲視窗及取樣式相位偵測器取代傳統的半速率相位偵測單元，可降低對稱佈局走線難度和電路消耗功率；另外，資料追鎖頻寬以Serial-ATA III中的規格為基底，並加入頻寬可調機制，使迴路頻寬擁有較大的資料追鎖範圍。在半速率取樣時脈與資料回復電路實現上，採用TSMC 0.13 μm 1P8M CMOS製程，供應電源為1.2 V，取樣速率為3 Gsps，經模擬驗證輸出回復時脈抖動為8.31 ps，並列輸出的回復資料抖動均小於16.3 ps。 According to process evolution, the volume of the data transferring between processor and memory cells is larger and larger. This progress making the conventional data bus can not deal with such huge rate. Hence, wide bandwidth transmitter and receiver become the trend of the next generation. The SERDES technology adopts cable or data bus as high speed serial interface. It applies from fiber communication to general computer interface. The clock and data recovery circuit designed in this thesis applies to 6 Gbps serial link system. The output of recovery data are two sets of 3 Gbps data stream in parallel. The dual loop phase selecting structure is composed of multi-phase phase lock loop and data recovery loop. The advantage of this architecture is that two loops are independent in each other. It can solve the conflict between jitter transfer function and jitter tolerance in single loop. In data recovery loop, it utilizes improved data delay window and sampling phase detector to replace conventional half-rate phase detector. It can simplify the difficulty in symmetrical layout and decrease the power consumption. Otherwise, the data tracking bandwidth is based on Serial-ATA III specification, and it equips with the function of tunable tracking bandwidth. Thus, the clock and data recovery circuit has larger data tracking range. In implementation of half-rate clock and data recovery circuit, it utilizes TSMC 0.13 μm 1P8M CMOS process. The power supply is 1.2 V and sampling rate is 3 Gbps. The peak to peak jitter of recovery clock is 8.31 ps, and the recovery data jitter is less than 16.3 ps by simulation verification.
Appears in Collections:	[電機工程研究所] 博碩士論文

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