隨著短距離無線通訊的演進，毫米波頻段逐漸受到重視及廣泛的應用，為了提升毫米波頻段低雜訊的訊號源，以提供準確的頻率及相關的高頻訊號處理，使用訊號倍頻及注入式鎖態的方式，可以改善在高頻操作下的訊號由於元件特性或是被動元件的品質因數所造成相位雜訊不良的問題。本論文頻段主要設計於60 GHz，透過WIN 0.15 μm GaAs pHEMT與TSMC 0.18 μm CMOS製程實現兩部份的電路。第一部份利用兩個交錯耦合對的架構，設計為20-60 GHz三倍頻BPSK調變器電路；在適當閘極-源極間偏壓的選擇，讓電晶體的操作點對於三階諧波有最大的輸出效率，並藉由高低準位的變換下使輸出能有BPSK的調變訊號。 第二部份使用注入式鎖態振盪器搭配二倍頻技巧，讓壓控振盪器產生60 GHz訊號，當振盪器受到外部訊號輸入時，為了平衡振盪條件，在鎖定後會有相位移的形成，將此特性運用在相位天線陣列中。本電路排列成2×2的振盪器陣列電路，在基頻注入鎖定時，相位雜訊在偏移中心頻率1 MHz時為-116 dBc/Hz，最大鎖態範圍為350 MHz，相位移能有-154˚至176˚的範圍。With the progress of short-range wireless communications, many development and applications are applied in millimeter-wave bands. In order to obtain a low phase noise of reference signal and an accurate operation frequency in millimeter-wave bands, using the frequency multiplier and injection-locked approach can improve the phase noise caused by the poor device characteristics or quality factor of passive in the high-frequency band. In this thesis, all circuits are designed in the 60 GHz band by WIN 0.15 μm GaAs pHEMT and TSMC 0.18 μm CMOS technologies. In the first part of thesis, the two cross-coupled pair are used to design a 20-60 GHz frequency tripler with functionality of BPSK modulator. The third-harmonic with low conversion loss can be achieved by choosing the proper bias on the transistor device, where the source bias changes alternately to transform the output phase with BPSK modulation. In the second part of thesis, a 60 GHz VCO used the injection-locked oscillator with a second-harmonic generation techniques. In order to balanced the oscillation condition when the oscillator is interfered by an external signal, the phase will shift when locking. The phase shift feature is further used in the phase antenna array. The design of a 2×2 oscillator array in implemented. When the fundamental frequency is injected, the maximum locking range is up to 350 MHz. The phase noise can be improved to -116 dBc/Hz at 1-MHz offset, and the phase can shift from -154˚ to 176˚ under a locking status.
