矽基板雜訊耦合與防護環設計分析 ; Si Substrate Noise Coupling and Guard Ring Analysis

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題名:	矽基板雜訊耦合與防護環設計分析;Si Substrate Noise Coupling and Guard Ring Analysis
作者:	顏志佑;Chih-yu Yen
貢獻者:	電機工程研究所
關鍵詞:	基板雜訊;防護環;substrate noise;guard ring
日期:	2010-07-20
上傳時間:	2010-12-09 13:52:51 (UTC+8)
出版者:	國立中央大學
摘要:	隨著科技的進步，積體電路的微小化，將數位與類比電路整合在同一晶片上是一個未來的趨勢，但類比電路會受到數位電路所產生的基板雜訊的影響而改變其特性，因此基板雜訊在積體電路設計是一個不可忽視的議題。本論文主要研究內容分為兩部分，第一部分為利用TSMC 0.18 μm CMOS製程設計一普遍應用於元件設計中，抑制雜訊的結構防護環，並觀察其在不同偏壓以及在低頻和高頻時的隔離度，並歸納出不同條件時的抑制能力。第二部分為基板雜訊對射頻電路耦合效應，由訊號產生器將不同頻率、振幅之方波訊號灌入到基板中，觀察雜訊對一操作頻率為21 GHz之電壓控制振盪器的輸出功率和相位雜訊的變化，當輸入的方波振幅和頻率越大，電路所受到的影響越大。在得知電路所受到的影響後，進一步的則是將防護環圍繞整個電路來抑制基板雜訊，並給予防護環適當的偏壓改變其抑制能力。Continuous scaling of CMOS technology has resulted in chips with digital and analog circuit integrating on the same chip. However, the performance of the analog circuits will degrade due to substrate noise generated by the digital circuits. Substrate noise is an effect that can no longer be ignored in integrated circuit design. This research content divides into two parts. First we proposed a novel structure as guard ring for device to suppress substrate noise by tsmc 0.18 μm CMOS technology. We applied bias to the guard ring and observed the isolation for low and high frequency. Finally we concluded the best condition for the isolation. The second part is substrate noise coupling effect to circuit. The effect of signal on the VCO was investigated by applied various magnitudes and frequency square signal to the substrate in term of output power and phase noise. The output power and phase noise was degraded for various magnitudes and clock frequencies of the square signal applied. Further, the suppression of the signal on the VCO by the global guard ring was demonstrated and compared for various guard ring bias schemes.
顯示於類別:	[電機工程研究所] 博碩士論文

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