| 摘要: | 在現今高速傳輸系統中，鎖相迴路(Phase-locked loop, PLL)及延遲迴路(Delay-locked loop, DLL)常被用來作為時脈倍頻與解決電路內的時脈歪斜(Skew)，在傳送接受器(Transceiver)的傳送端(Transmitter)中，時脈同步電路常被用來提供給序列器(Serializer)，使資料可以從並列轉成串列的輸出，而在接收端(Receiver)中，除可以提供給時脈資料回復電路(Clock and data recovery circuit, CDR)所需要的參考時脈以外，其也可以提供給解序列器(Deserializer)所需要的時脈，來使得資料從串列的轉成並列的形式。在太陽能電池供應的電壓下，其電壓為0.5 V，因此低電壓與低功率消耗的積體電路也變的越來越重要。在高速系統中，資料從傳送端傳送出來，並且經由通道來傳送，但通道的損失將造成資料在傳送時遇到符元干擾(Intersymbol interference, ISI)的現象，而使得資料的眼圖關閉，因此在接收端加上等化器(Equalizer)可以用來補償通道的損失，使接收端可以正常的接收資料。 首先本論文提出了一個低抖動(Jitter)的鎖相迴路，並且可應用於10 Gbps高速有線傳送接收機，其可以提供所需的2.5 GHz，8個相位之時脈，此鎖相迴路中的可變延遲元件(Variable delay cell, VDC)，可以使用在電壓控制器中(Voltage-controlled oscillator, VCO)去達到較寬的可調頻率範圍，以及較低的電壓控制增益(KV CO)。而此鎖相迴路也加入了自我校準的機制(Self-adjustment circuit, SAC)，其可以保護鎖相迴路使其不受製程、電壓與溫度飄移的影響。此鎖相迴路使用了0.13 μm CMOS製程，在2.5 GHz的操作頻率下，其可以達到2.83 ps(rms)的抖動量，並且功率消耗為21 mW，晶片核心面積為0.08 mm^2。 接著本論文針對於低功率消耗的應用設計了一個無電感式的鎖相迴路，其可以應用於太陽能電池供應之0.5 V電壓下，其中提出了一個充放電幫浦(Charge pump, CP)，此充放電幫浦可以達到低漏電流與高速的操作。並且也提出了一個低電壓的電壓控制振盪器(Low-voltage-controlled oscillator, LV-VCO)，其由四級的延遲元件與一個低電壓分段式電流鏡(Low-voltage segmented current mirror, LV-SCM)所組成，其可以達到低的電壓控制增益，寬操作頻率範圍，以及較佳的線性度。低電壓分段式電流鏡利用控制電晶體的基極端，因此可以產生較多的電流。此鎖相迴路利用標準的90 nm CMOS製程，並且使用正常的VT值元件來實現。此鎖相迴路在2.24 GHz時輸出抖動為2.22 ps (rms)，並且在1 MHz的偏移下相位雜訊為−87 dBc/Hz。功率消耗為2.08 mW，晶片面積為0.074 mm^2。 為了解決資料經過通道後所造成的符元干擾，最後本論文也提出了一個類比可適應性的等化器去解決通道所造成的資料損失。此類比等化器利用一個低電壓的零點產生器(Low-voltage zero generators, LVZGs)去產生一個高頻的增益補償，並且不需要使用到被動的電感元件，因此可以節省面積的消耗。除此之外，也使用了頻譜平衡技巧(Spectrum-balancing technique)，因此不需要使用到Slicer的電路。在功率偵測器(Power detector)方面，結合了電流操控技巧(Current steering techniques)與預先放大器(Pre-amplifier)電路，因此可以加大偵測的電壓擺幅。此設計的類比等化器可以在2.5 GHz時補償14 dB的通道損失，並且其功率消耗在1.6 V供應電壓下為17.6 mW，輸出之電壓擺幅為560 mV (pk-pk)，面積的消耗為0.1 mm^2，輸出之峰對峰值抖動為0.28 UI。 在本論文中所提出之時脈同步電路可以應用於高速之有線傳送接收機內，去提供時脈及相位給各個電路來使用，並且類比等化器可以去補償高速資料在通過通道時所造成的資料損失。 In high-speed transceivers, phase-locked loops (PLLs) and delay-locked loops (DLLs) are used as clock generators to avoid clock skew. In the transmitter, the clock synchronization circuits are used to provide the clock signal to the serializer. Therefore, the data can be transmitted from the parallel data to the serial data. In the receiver, the clock synchronization circuits provide the reference clock signal to the clock and data recovery circuit. In addition, the clock synchronization circuits provide the clock signal to the deserializer. Therefore, the data can be transferred from serial data to parallel data. The solar battery provides the 0.5 V supply voltage. Therefore, low-voltage and low power consumption integrated circuits have become more and more important. In high-speed systems, the data is sent from the transmitter and passes through the channel. The channel loss causes the inter-symbol interference (ISI) when the data passes through the channel. The eye diagram of the data is closed. Therefore, the equalizer can be used to compensate for the channel loss in the receiver so that the receiver can receive the data correctly. First, a low-jitter PLL is proposed for 10 Gbps high speed wired-line transceiver applications. The PLL provides 2.5 GHz, eight-phase output clock to the transceiver. The new variable delay cell (VDC) for the voltage-controlled oscillator (VCO) achieves a wide-range of output frequencies and a low noise sensitivity with low KVCO. The PLL consists of a self-adjustment circuit (SAC), which protects the PLL from variations in the process, voltage and temperature (PVT). The PLL is implemented in 0.13 μm CMOS technology. The PLL output jitter is 2.83 ps (rms). The total power dissipation is 21 mW at a 2.5 GHz output frequency, and the core area is 0.08 mm^2. Next, an inductorless PLL is proposed for low-power consumption applications. The PLL is suitable for the solar battery, which provides a 0.5 V supply voltage. A new charge pump (CP) circuit affords a low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves a low voltage-controlled oscillator gain (KVCO), a wide tuning range, and good linearity. The LV-SCM generates more current within a small area by switching the body rather than the gate. The PLL is implemented in standard 90 nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms). The phase noise is −87 dBc/Hz at a 1 MHz offset from a 2.24 GHz center frequency. The total power dissipation at a 2.24 GHz output frequency, and with a 0.5 V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm^2. To solve the ISI effect while the data passes through the channel, an equalizer can be added in the receiver. Finally, this dissertation also proposed an analog adaptive equalizer to compensate for the channel loss. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency gain boosting without inductors. The spectrum-balancing technique eliminates the need for a slicer. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. The equalizer can compensate for the channel loss of 14 dB at 2.5 GHz. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (pk-pk). The occupied area is 0.1 mm^2 (including output buffers), and the output peak-to-peak jitter is 0.28 UI. In this dissertation, the proposed clock synchronization circuits can be used in high-speed wired-line transceivers. They provide a clock signal and phases to other circuits for correct operation. The analog equalizer compensates for the channel loss when the high-speed data passes through the channel. |
