分析空間平滑性和時間連續性於SoC監視系統中前景偵測之加速; Exploring Analysis of Spatial Smooth and Temporal Continuity for Foreground Detection Accelerating on Surveillance SoC System

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/48610

Title:	分析空間平滑性和時間連續性於SoC監視系統中前景偵測之加速;Exploring Analysis of Spatial Smooth and Temporal Continuity for Foreground Detection Accelerating on Surveillance SoC System
Authors:	李思彥;Sz-Yan Li
Contributors:	電機工程研究所
Keywords:	物件標記追蹤;前景擷取;消除雜訊;智慧型監視系統;intelligent surveillance systems;OR1200-based SoC
Date:	2011-08-29
Issue Date:	2012-01-05 14:59:14 (UTC+8)
Abstract:	當今，智慧型監視系統嘗試著增加高解析度攝影機的數量，並且達到及時運算的能力。但為了達到這些能力，中央伺服器將會大幅度的增加運算負擔。為了減少伺服器的運算負擔，我們提出了一個想法，讓攝影機本身就擁有相當程度的運算處理能力，而為了能讓整體成本下降，我們必須開發一個低成本的智慧型處理核心，本篇文章提出了一個低成本，並且以OR1200處理核心為基礎的系統晶片設計。我們提出的系統晶片包含了三個專用的硬體加速模組和一顆開放源碼的中央處理核心，其中三個硬體加速模組為前景擷取、消除雜訊和物件標記追蹤的硬體模組，其還可利用中央處理核心去使用硬體加速模組處理後的資訊，來做軟體上的功能開發。並且，在此篇論文裡，我們提出了簡化前景擷取的演算法。我們利用影像擁有的空間平滑性和時間連續性的特性，來加速前景擷取和記憶體頻寬的下降，而跟之前開發的前景擷取演算法做比較，我們提出的演算法在模擬時間上在室內監控環境下，下降了61.99% ，而在室外監控環境下，下降了56.99%。在此篇論文裡，我們使用了pipelining和平行處理的技術，來加速我們的SoC設計，提高處理能力。最後，我們提出的SoC晶片可達到HD720p的即時處理能力，而其邏輯閘的數目為12萬8746。整體的晶片面積為653232毫米平方。工作頻率，硬體模組為31.7MHz，中央處理器為300MHz At present, intelligent surveillance systems attempt to raise amount of high resolution cameras, for achieving on real-time process. Those systems stupendously increase the computational load on central server. For reducing the burden of sever, we propose that let the camera is capable of analyzing information. For total coast reducing, we need to develop a low coast system. This paper proposes a low cost OR1200-based SoC design. The proposed architecture consists of foreground detection accelerator, noise reduction accelerator, object level tracking accelerator and a programmable processor for software development. In this paper, we propose a method to simplify foreground detection. We utilize the characteristic of video, there are spatial smooth and temporal continuity, to accelerate the foreground detection and reduce memory bandwidth. Compare the computational time of previous work, the experimental result of simulation shows the computational time reduces 61.99% and 56.99% on indoor and outdoor scene separately. In SoC design, pipelining and parallelizing techniques are largely used to increase the throughput. The total gate count is 128.746K, the total cell area is 653232 mm2 and the operation frequency for real-time HD720p sized sequence processing is 31.7 MHz and 300MHz for accelerators and OR1200 RISC processor respectively.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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