隨著半導體製程的不斷進步，晶片上元件尺寸與導線寬度也逐漸的微縮，這 樣的改變，使得元件之間的參數變異和不匹配關係加劇，也引進了許多難以控制 的製程變動問題。在現今的類比積體電路中，電路的效能受到元件間的參數變異 之影響，而元件的參數值又隨著各種不匹配的效應而改變。因此，如果想使電路 產生預期的理想效能表現，就必須妥善的處理電路中的不匹配。 本論文提出了對於電容元件不匹配的處理方法，從相關係數的角度出發，利 用元件的空間相關特性，評估電容擺放的好壞，再將不匹配的效應由多項式轉換 為矩陣的形式。透過矩陣相乘的描述方式，可以把每個對電容陣列造成影響的獨 立算子，定義成不同的特徵矩陣來分別探討。最後再用階層化的方法，將此理論 應用在更大的n 階矩陣上。 相較於使用多項式的描述方式，運用矩陣的形式來討論不匹配效應，可以得 到許多好處：不但可以用此方法來處理任意型式的獨立算子，也因為矩陣排列呈 現左右對稱的狀態，使得計算時會更佳簡便。此外，在電容排列是1：1 及方陣的 情況下，將可用階層化的方式擴展電容陣列，並推展至n 階。 As the evolution of semiconductor process technology, the size of elements and the width of wires on chips are reduced. These changes result in some uncontrollable alterations of process and aggravate the mismatch and parameter variation of components. Nowadays, the performance of analog integrated circuits is influenced not only by the parameter variation of components but also by the mismatching effects. That is to say, the approach of mismatch effects becomes a critical issue for better anticipated performance. This thesis proposes a method for improving mismatch of elements. In this method, we estimate capacitance placement by spatial correlation and exchange mismatch effect from polynomial term to matrix term. For independent operators which influence capacitance arrays, we define them as characteristic matrices. Furthermore, this method could also be used to the general N order matrix in hierarchical structure. Instead of polynomial form, we use matrix form to discuss mismatching effects. This method has two benefits: the ability to handle any types of independent operators and the easier calculation property which derives from the symmetrical terms. Besides, we could use hierarchical structure to expand capacitance array, if the placement are both two targets and 1:1 segments.
