本論文提出一個操作在4 GHz、擁有10個相位輸出之全數位式鎖相迴路之單晶片系統設計。此鎖相迴路所運用之多重相位數位控制振盪器採用三態反向器組成的迴圈，以獲得高頻率輸出及寬範圍操作。所使用之時間數位轉換器重複利用振盪器的多相位輸出來對時間差值作取樣，因此可大幅減少面積消耗。並加入了一個時間放大器，來增加時間數位轉換器的解析度。另外，藉由一個頻率偵測器，加速數位控制振盪器在選擇頻段下的運作，增加鎖相迴路中頻率追鎖的速度。因此，本鎖相迴路能滿足可攜式電子產品應用之需求。 本論文之全數位式鎖相迴路使用TSMC 90 nm 1P9M CMOS製程實現晶片，其操作頻率範圍可從3 GHz到4.2 GHz。電路在操作頻率為4 GHz時，功率消耗為52 mW，而輸出訊號之最大峰對峰值時間抖動量為12.14 ps (4.86 %)，方均根抖動量為1.44 ps。整體晶片面積為510 × 590 um2，核心電路的面積為140 × 220 um2。 A 4-GHz 10-phase all digital phase-locked loop (ADPLL) is proposed for system-on-chip (SoC) systems. The proposed multiphase digital controlled oscillator (MP-DCO) adopts the tri-state inverter loop scheme to obtain the higher operating frequency and wide operation range. The MP-DCO outputs are used to be Time-to-digital Converter (TDC) sampled clock and sample the time difference. Therefore, the reused MP-DCO output can reduce the area cost of the TDC. Time amplifier (TA) can extend the timing resolution of the TDC. The frequency acquisition can achieve the fast locking time using frequency detector (FD) and multi-band operation range of the MP-DCO. Thus, this clock generator is suitable for portable products and mobile applications. The experimental chip was fabricated by TSMC 90 nm 1P9M CMOS process. The measurement results show that the operation range is from 3 GHz to 4.2 GHz, and the power consumption is 52 mW at 4 GHz. The peak-to-peak jitter and RMS jitter are 12.14 ps and 1.44 ps at 4 GHz, respectively. The whole chip area is 510 × 590 um2, and the core area is 140 × 220 um2.
