High Efficiency Architecture Design of Real-Time QFHD for H.264/AVC Fast Block Motion Estimation

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/52071

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52071

Title:	High Efficiency Architecture Design of Real-Time QFHD for H.264/AVC Fast Block Motion Estimation
Authors:	Tsai,TH;Pan,YN
Contributors:	電機工程學系
Keywords:	DIAMOND SEARCH ALGORITHM
Date:	2011
Issue Date:	2012-03-28 10:14:43 (UTC+8)
Publisher:	國立中央大學
Abstract:	Motion estimation (ME) in the MPEG-4 AVC/JVT/H. 264 video coding standard employs seven permitted block sizes to improve the rate-distortion performance. This novel feature achieves significant coding gain over coding a macroblock using the fixed block size. However, ME is computationally intensive with the complexity increasing linearly with the number of the allowed block sizes. This paper presents an architecture for a combined fast ME algorithm with the predict hexagon search (PHS) and the edge information mode decision (EIMD). The EIMD algorithm utilizes edge information to predict the best block size quickly and precisely. The PHS algorithm searches the best motion vector efficiently. The analytical results reveal that the EIMD+PHS algorithm is 2.4-25 times faster than other popular fast ME algorithms. Additionally, the EIMD+PHS algorithm is 600-2000 times faster than JM10.2, and the peak signal-to-noise ratio degradation is less than 0.15 dB. The proposed architecture applies a large search range and low operation frequency as compared with other popular ME architectures. The proposed architecture only needs 19.4 MHz operating frequency to achieve real-time execution for the general specification of the standard-definition television (720 x 480) used with four reference frames and the search range of 256 x 256. The proposed architecture only requires 116.6 MHz operating frequency to achieve real-time execution for the ultrahigh specification of the quad full high definition (3840 x 2160) used with one reference frame and the search range of 256 x 256. The gate count of the proposed architecture is 300 K, and the memory usage is 12.6 kB.
Relation:	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	326	View/Open

社群 sharing

Loading...