自從1970年代開始，金屬互連線寄生參數效應的相關研究逐漸受到重視，到了21世紀初期，隨著先進製程的最小線寬以及積體電路的特徵尺寸持續微縮，寄生效應對積體電路運作時產生的雜訊干擾、功率損耗、訊號傳遞延遲等效應，皆因製程微縮效應的關係，開始對電路功能的可靠度造成更顯著的影響。因此，如何在積體電路設計的過程，考量到製程變異，並且可分析金屬互連線產生的相關寄生效應對積體電路的影響，已成為積體電路設計與量產可行性研究領域中一項具有挑戰性的重要議題。本研究針對陣列區塊電容具有規律性的繞線風格，企圖提出具有物理模型與定則模型兩種特性的雞尾酒式寄生電容參數預估法。藉由使用物理模型法分析陣列區塊電容具有特定繞線模式的互連線物理結構，進而取得精確的寄生電容係數，再輔以定則模型法的公式分析具規則性的陣列區塊電容，以預估寄生電容參數值。研究結果顯示，針對2個電容所構成的陣列區塊電容，應用雞尾酒式寄生電容參數預估法進行預估後，與佈局寄生萃取工具萃取的寄生電容值比較過後，電容上極板的寄生參數平均誤差範圍在4.32%以內，電容下極板的寄生參數平均誤差範圍在2.84%以內。對於陣列區塊電容而言，應用雞尾酒式預估法能有效率且精確地計算出寄生電容參數值，以供類比積體電路設計者於電路設計過程事先評估電容值變異對電路效能的影響。Since the beginnings of 1970s, much attention of the relevant research for the parasitic effects of interconnect has been attached. By the early 21st century, with the continuous evolution of semiconductor manufacturing technology, the minimum line width and the feature size of integrated circuits keep scaling down. Because the physical effects from IC scaling, the effects related to parasitic effects like noise interference, power consumption and signal propagation delay have begun to make some increasing impact on the reliability and function of IC. Therefore, how to take the variation of manufacturing process and parasitic effects of interconnect into the design flow of IC has become a challenging study issue in the field of design for manufacturability of IC.The research focuses on how to propose a cocktail estimation of parasitic capacitances in array block capacitors with the properties of physics-based model and rule-based model. By means of utilizing physics-based model, we can conduct an analysis of interconnect structure on the routing style of array block capacitors. As a result, we will obtain capacitance coefficients which are more accurate in order to estimate parasitic capacitances in array block capacitors with the aid of equations in rule-based model.The main results of the study show that the tolerance range of estimation for top plate of array block capacitors is fewer than 4.32%. Similarly, the tolerance range of estimation for bottom plate of array block capacitors is fewer than 2.84%. These findings suggest that cocktail estimation of parasitic parameters in array block capacitors can calculate parasitic capacitances efficiently and accurately. Therefore, cocktail estimation can be used by Analog IC Designer to evaluate the performance deviation of capacitors affected by parasitic effects.
