低成本類比數位轉換器自動測試機台研究;The Study on Low Cost Automatic Test Equipment (ATE) Implement in Analog to Digital Convertor (ADC) Test Solution

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題名:	低成本類比數位轉換器自動測試機台研究;The Study on Low Cost Automatic Test Equipment (ATE) Implement in Analog to Digital Convertor (ADC) Test Solution
作者:	蔡政憲;Tsai,Cheng-hsien
貢獻者:	電機工程研究所碩士在職專班
關鍵詞:	半導體元件測試;線性度;Linearity;IC test
日期:	2012-07-20
上傳時間:	2012-09-11 18:53:56 (UTC+8)
出版者:	國立中央大學
摘要:	回顧台灣半導體產業發展史自引進積體電路(Integrated Circuit, IC)封裝測試技術(Assembly and Test)迄今已有40年歷史，在政府有計畫的輔導、推動以及業界多年的經營，從上游晶圓材料到IC設計業、製造業、封裝業、測試業等，產業結構可謂相當完整，產值與成長率都有十分顯著的成績。近年來IC的功能日趨複雜且強大，速度上由1970年代的百萬赫茲(MHz)頻率到現在的幾十億赫茲(GHz)頻率，因此產品測試已是十分重要。從產品開發週期，測試成本(Cost of Test, COT)也日趨高漲。為了符合測試需求，IC產品性能的提升使業界對自動測試機台(Automatic Test Equipment, ATE)的性能也越來越講究，相對投資更高的COT。在上述的背景下，本論文主在研究如何降低COT且增加成品測試(Final Test)，本篇論文架構將包含下列方向：1.低COT ATE軟硬體(Software and Hardware)結構研究2.研究測試產能(Productivity)提升、效率改善以降低測試成本3.類比轉換數位器(Analog to Digital Convertor, ADC)線性度測試學理之創新〝雙碼關係(Relationship Between a Pair of Codes, RBPC)〞及測試程式的實現。本文目的在於研究低COT技術應用在ATE測試流程以改善測試效率、提升測試品質以及產能提升建立低測試成本環境。While reviewing the history of Taiwan's semiconductor industry, the assembly and test technology of integrated circuit (IC) had been introduced to Taiwan for 40 years. Due to the government’s great support and lots of companies invested funds and human resource on the semiconductor industry over years, Taiwan has well developed the matured semiconductor technology including wafer process manufacturing, IC design, assembly and test infra-structure. Where the industrial structure is quite complete and their output value and growth rate are very significant. The functions of IC become increasingly complex and powerful recently. In 1970s, from the operation frequency at megahertz (MHz) to gigahertz (GHz), therefore the IC product testing becomes important. From the product development cycle, testing costs (Cost of Test, COT) are becoming increasingly high. In order to meet the testing demand, due to IC product performance complexity and precision, then we require Automatic Test Equipment (ATE) with higher specifications relative to the investment of high COT.The purpose of this paper is a test methodology to reduce the COT and increases the capacity of the final test (FT) production. The thesis contains the following section:(1) Structure of the low COT ATE hardware and software (2) Research of the testing capacity (productivity) enhancement and improve efficiency to reduce COT.(3) Analog converter Digital’s (ADC’s) linearity innovation test based on "relationship between the pair of codes, RBPC" and its test program.
顯示於類別:	[電機工程學系碩士在職專班] 博碩士論文

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