本論文以傳統Sorted QR分解來分析其各級排序造成的能量分佈情形，並且探討排序後對於後端樹狀解碼中每一層所造成的影響，之後再依據我們的搜尋方式將效能較差的排序級數跳過，找到一個複雜度最低且錯誤率無明顯上升的排序組合。在QR分解的架構中我們採用Systolic Array的架構來達到較高的產出量，並且加入輸入控制電路使其能夠支援不同天線數的QR分解，使硬體使用率盡可能地提高。相較於傳統Sorted QR分解，我們所提出的方法除了有較低的排序複雜度外，在於運算時間上也能有相當的改善，我們以所提出的方法設計我們的電路架構使其能更有效率運算。最後本論文使用SMIMS VeriEnterprise Xilinx FPGA板驗證其電路功能，並且以TSMC-90 nm製程實現所提出之QR分解電路。This thesis is dedicated to analyze the circumstance of energy distribution which is caused by different sorting stages with conventional Sorted QR decomposition. It also discusses the effect of each stage of Sphere decoder after sorting. Furthermore, according to our searching methods, tries skip the inefficient sorting stages and then find out a sorting combination which is less complicated and which doesn’t have an apparently rising sorting combination.In the structure of QR decomposition, we adapt Systolic Array structure in order to achieve a higher production, and also add input control for supporting different antenna mode of QR decomposition for the sake of raising the utility rate as possible as we can. In comparison with the conventional Sorted QR decomposition, our method is not only less complicated, but also has a great extent of improvement of operating time. We design our architecture with this method for having a more efficient operation.In the end, we use MIMS VeriEnterprise Xilinx FPGA to verify circuit function, then we use TSMC-90 nm to implement our circuit.
