在系統單晶片(System on chip, SoC)的設計中，將不同功能的類比、數位或是射頻電路都整合在一顆晶片內，每個區塊電路所需要的電壓往往都不一樣，系統單晶片的供應電源往往是單一電壓，於是就需要電壓轉換器來將供應電源轉換成每塊電路需要的供應電壓。有著低功率、輸出漣波電壓很小、抗雜訊等優點的低壓降線性穩壓器就常常被應用在轉換電壓上。本論文提出一套低壓降線性穩壓器自動化設計的流程，依靠非線性規劃(Nonlinear programming)、gm/ID的設計概念以及電壓驅動的方法改善傳統幾何演算法的精準度以及效率。誤差放大器(Error amplifier)和低壓降線性穩壓器可以在自動化流程中同時做互相考慮以及最佳化的動作，使整體電路的成本減少。整個流程以Matlab和Hspice來實現，並整合成一個完整的程式。從實驗數據跟傳統的幾何演算法設計流程做個比較，本論文所提出的方法，可以提高公式精準度，同時更可以在相同的規格下，在短時間內找出優於傳統幾何演算法的電路設計。In typical SoC (System on chip, SoC) designs, analog, digital and RF circuits are integrated in a single chip. Because the supply voltage of each circuit block may not the same, voltage converters are often required to generate the required supply voltage of each block from the outside power source. Due to its low power, small ripple and low noise properties, low-dropout linear regulators (LDO) are often used in SoC chips. This thesis proposes a design automation process for optimal sizing of low dropout linear regulator. Based on the nonlinear programming and gm/ID design concept, a bias-driven methodology is adopted to improve the accuracy and efficiency of the traditional approach based on geometric programming. The device in the low dropout linear regulator and its error amplifier are both considered in the optimization process for reducing the overall circuit cost. The proposed automation process has been implemented with Matlab and Hspice. As demonstrated in the experiments, the proposed approach can achieve the required specifications with the shortest computation time and the lowest hardware cost compared to previous approaches.
