在通訊與多媒體的快速發展之下，對於高傳輸速率與高容量傳輸系統的需求也愈來愈高。隨著高傳輸速率的無線通訊市場的大量增加，積體電路設計的操作頻率也逐漸往微波與毫米波頻段發展。論文第一章將簡短介紹射頻發射機與光通訊系統的傳輸系統。第二章第一部份先整理1970年迄今介紹FET等效小訊號模型的相關文獻，將單閘極元件模型歸納為7種主要類型。第二部份整理歷年來介紹關於雙閘極元件等效小訊號模型的文獻，歸納為4種主要小訊號模型，而雙閘極元件由於可以等效為兩個單閘極元件疊接，因此可以設計應用在高增益及寬頻的系統上。為了驗證單閘極及雙閘極元件模型，將於第三章應用第二章介紹的模型萃取方法，以砷化鎵0.5 μm增強/空乏模式電晶體元件進行設計及量測，分別重建2組單閘極小訊號模型與1組雙閘極元件模型。西元1948年E. L. Ginzton提出的分佈式放大器，由於擁有高增益頻寬比，因此在寬頻放大器的應用上佔有舉足輕重的地位。第四章以一組雙閘極與單閘極元件進行疊接架構作為增益單元，應用電感提升與m衍生低通濾波器技術來增加高頻增益，最後再應用主動負載提供偏壓來減少直流功率損耗。第五章以砷化鎵0.5 μm HBT-HEMT製程設計一組以HEMT-HBT串接達靈頓對為增益單元，半電路為串聯單級分佈式放大器的差動達靈頓串聯單級分佈式放大器。相較於半電路為傳統式分佈式放大器的差動放大器，使用串聯單級分佈式放大器作為差動放大器的半電路能擁有更佳的共模拒斥比特性。第六章第一部份使用矽金氧半場效電晶體的0.18 μm SiGe BiCMOS製程，以NMOS與HBT兩種不同電晶體作為增益單元，應用疊接架構來降低輸入端等校雜散電容，並減少米勒效應(Miller effect)對電路的影響，最後設計出一組高頻寬的傳統分佈式放大器。由於串聯單級分佈式放大器的輸出功率受限於輸出端電晶體的大小，因此在第二部分使用矽金氧半場效電晶體的90 nm CMOS製程，以傳統分佈式放大器作為串聯單級分佈式放大器的輸出級電路來增加串聯單級分佈式放大器的輸出功率，設計出一組CSSDA-CDA組合式分佈式放大器。第七章為結論，為本論文所做的研究做一個總結。The demands for high-speed and high-capacity transmission systems rapidly increase due to the development of multimedia communications in recent years. The increasing trend in modern wireless communications for high data-rate applications, especially for the analog and RF front-end is pushing the integrated circuits to operate in microwave and millimeter wave. In this thesis, the introductions of RF transceiver and optical communication are given in Chapter 1. Since the device model of single-gate and dual-gate FETs are essential in the design of microwave circuits, seven kinds of single-gate small signal model and four kinds of dual-gate small signal model are generalized in Chapter 2. To analyze the characteristics of a 0.5 μm enhancement/depletion-mode (E/D-mode) GaAs process, two single-gate and a dual-gate small signal models based on the method introduced in Chapter 2 have been presented in Chapter 3. The distributed amplifier (DA) is well known to be a good topology for ultra-wideband design after it was proposed by E. L. Ginzton in 1948. In Chapter 4, two conventional DAs with inductive peaking and m-derived technique, and a cascode configuration with a single-gate device and a dual-gate device is adopted for the gain cell to have the property of wideband and over 10 dB small-signal gain. An active load technique is used for the DC bias of the DA design to achieve low DC consumption. A Darlington differential cascaded single-stage DA (CSSDA) using a GaAs 0.5-μm HBT-HEMT process is presented in Chapter 5. To compare with the conventional DA (CDA), the CSSDA topology has better common-mode rejection ratio. To achieve the broadband design, two DAs with inductive peaking technique using Si-based process are presented in Chapter 6. In the first section, a CDA using 0.18 μm SiGe BiCMOS process and a cascode NMOS-HBT topology is used for the gain cell to decrease the Miller effect. The proposed DA has an average small-signal gain of 8.2 dB and a 3-dB bandwidth from DC to 31 GHz. To improve the output power of the CSSDA, a CSSDA-CDA composite DA using 90 nm CMOS process has been presented in the second section of Chapter 6. Finally, the conclusion is given in Chapter 7.
