本論文將介紹經由台積電90奈米製程實作，應用於室內高傳輸率無線通訊系統的多輸入多輸出正交分頻多工基頻收發機。接收機支援QPSK、16QAM與64-QAM的星座圖且空間多工達四根天線。此系統有三種操作模式，分別對應到128、256與512三種不同的FFT點數。接收機的部分，整合了同步偵測、通道估測與多輸入多輸出訊號的解碼三個主要功能區塊，使用了24顆大大小小的記憶體，為達到節省硬體，其中有5顆記憶體屬共用記憶體。我們在時域上結合符元邊界時間偵測與小數載波頻率偏移估測模組。接收訊號先進入符元邊界時間偵測與載波頻率偏移估計模組來得到適當的FFT操作區間和最初的載波頻率偏移估測值。訊號被FFT單元轉換到頻域之後，我們也設計了在頻域上的殘餘載波頻率偏移與取樣時間偏移追蹤裝置來補償殘餘載波頻率偏移與時間頻率偏移以避免其嚴重破壞系統的效能。透過長前置序列來進行通道估測動作，緊接著做一次排序的QR分解。如此一來，就可以將前置作業完成的訊號送入最佳K值球型解碼器去得到空間多工的使用者資料。我們也提供達到系統效能的模擬結果，使用TSMC 90nm製程，合成晶片邏輯閘個數為1.034MGE+835kbit，總消耗功率為335mW，後佈局模擬結果得知，系統操作在160MHz的取樣頻率下，可以達到2.592Gbps的傳送速率。In this thesis, implementation of a MIMO-OFDM baseband receiver by TSMC 90nm process for indoor highthroughput wireless communication systems is presented. The receiver supports QPSK, 16QAM and 64-QAM constellation and spatial multiplexing up to four antennas. The system has three operation modes corresponding to different FFT sizes of 128, 256, and 512 points. At the receiver, three main functional blocks of synchronization, channel estimation and MIMO detection are integrated at the receiver. And 24 memories are used. For reducing hardware complexity, five memories are shared. We incorporate symbol timing detection and carrier frequency offset (CFO) acquisition modules in the time domain. The received signals first enter into the symbol timing detector and CFO estimator to acquire an adequate FFT window and an initial CFO estimate. After the signals are transformed to frequency domain by the FFT unit, the subsequent CFO and sampling clock offset (SCO) tracking mechanism is also designed in the frequency domain to compensate the residual CFO and SCO errors to prevent from their severe destruction of the system performance. The channel estimates are then derived from the long preamble and are subsequently processed by the one-time sorted QR decomposition unit. Thereafter, the pre-processed signals are sent to the K-best sphere decoder to retrieve the spatial multiplexed user data. Simulation results are provided to show the satisfying system performance. The design is implemented in TSMC 90nm CMOS technology. It has gate count of 1.034M and uses memories of 835 Kbits. Total consumption power is 335mW. From post-layout simulation results, the system can work at 160MHz sampling frequency, which is capable to offer 2.592 Gbps transmission rate.
