| 摘要: | 近年來由於多媒體應用的普及使得資料存取的需求量增加，為了滿足更高速的資料傳輸頻寬並且降低成本，串列連結技術的應用已經普遍流行。此外，隨著電子裝置的操作頻率日趨提高，電磁干擾效應(EMI)越來越嚴重。在時脈產生電路中，由於集中的能量所造成的電磁干擾也將成為介面傳輸系統中的主要雜訊來源，因此為了降低電磁干擾效應，展頻時脈技術已廣泛的應用於時脈產生器中。本論文在TSMC 90 nm CMOS製程下提出了一應用於6-Gb/s有線傳輸且具有3-tap前饋等化器之串列發射器。隨著資料傳輸速率上升並且達到每秒兆位元的速度，有限頻寬的通道對於訊號傳遞的衰減已造成嚴重的衝擊，相對的，輸入/輸出緩衝器的設計也將面臨著嚴峻的考驗。另外，當高速資料經過通道傳輸時，由於及膚效應以及通道的介質損耗將使得接收端的資料造成嚴重的符際干擾(Inter-symbol Interference, ISI)。為了解決上述的問題，本論文除了實現一可將低速並列資料轉換成高速串列資料之樹狀串列器，並在輸出端亦加入了可消除前、後標記(Pre-cursor, Post-cursor)之3-tap的前饋等化器。前饋等化器係利用數位濾波器的原理，將資料延遲的總和作為輸出並使得輸出訊號達到預先失真的效果，在經過通道損耗後仍可獲得張開的資料眼圖。除此之外，高速的資料傳輸同時面臨著電磁輻射干擾效應影響，本論文利用一操作於6 GHz且具有相位補償之展頻時脈電路來降低傳輸資料之峰值功率。本展頻時脈電路分別由一鎖相迴路以及一延遲鎖相迴路所組成，此架構可免於頻寬外之量化誤差所影響以及數位雜訊之耦合干擾。經由模擬驗證，216-1之隨機資料通過39.36英吋FR-4通道 (16.6 dB損耗)，在6-Gb/s操作下補償後接收端前之眼圖的峰對峰值抖動為35.28 ps (資料眼寬為0.788 UI)，同時在5000-ppm的頻率偏移下具有24 dB的EMI衰減量。PISO和SSCG的核心面積消耗晶片面積約0.07和0.13 mm2，而功率消耗分別為61.2 mW和56.2 mW。Recently, owning to the requirement of the enormous data storage in the multimedia application, the serial link technique, satisfying with the higher data bandwidth, becomes the popular scheme as well as shows the advantage of low cost. In addition, as the electrical devices increase the operation frequency, the problem of electromagnetic interference (EMI) becomes sever. Thus, the EMI steaming from the concentrated peak energy of the clock generator will interfere with the other equipments. Accordingly, the spread spectrum clock generator (SSCG) is commonly used to reduce the EMI.A 6-Gb/s, 90-nm transmitter incorporating the three-tap feed-forward equalizer (FFE) is presented for the wire line communication. As the data rate rises up to mutigigabits per second, the impact of the limited bandwidth of the channel on the signal degradation has becoming severe with respect of the I/O buffer design for data transmission. Hence, the induced problem, which is the so-called inter-symbol interference (ISI), is mainly caused by skin effect and dielectric loss of the channel while transmitting the high speed random data. To overcome such issue, this study implements a tree-type parallel-in-serial-out (PISO) serializer, and the three-tap FFE, which consists of the pre-, main-, and post-tap, respectively, to pre-emphasize the serial data at the Tx output. The operation principle of the FFE resembles the FIR filter theory. The FFE pre-distorts the low frequency component of the data stream by the sum of each current weighting, which is controlled by the symbol-spaced data. In other words, such operation seems to pull up the high frequency component of the data in advance. Accordingly, via the predicted channel loss, the eye could be still opened at the Rx terminal. In addition, for the radiation issue of EMI, the 6-GHz phase-compensated SSCG is used to spread the peak power of the transmitted data. Such architecture is composed of DLL and PLL, showing the immunity to out-of-band quantization error and digital noise coupling. Thus, through a 39.36-in FR4 PCB trace with a 16.6-dB loss, the simulated peak-to-peak jitters of the 6-Gb/s, 216-1 random bit data is 35.28 ps (i.e., the eye width is 0.788 UI) at the Rx terminal, as well as the EMI is approximated to 24 dB with a 5000-ppm frequency deviation. The chip core area of the PISO and SSCG occupy 0.07 and 0.13 mm2, respectively. The power consumption are 61.2 mW and 56.2 mW at supply of 1.2 V. |
