單電子電晶體既具有高電荷靈敏度以及低功率消耗之潛能優點，亦是元件尺寸不停微縮的趨勢下所因應而生之量子元件。本論文目的是藉由改進本研究室前一代平面式單電子電晶體之缺點，並且重新設計，進而改善元件電特性與提升良率。在此篇論文中，我們將針對平面式的鍺量子點單電子電晶體的研製以及電流特性的分析作深入的探討研究。首先在製程上，我們先利用一奈米孔洞的製作來達成量子點的精確定位，之後利用選擇性熱氧化的方式在孔洞中心形成單顆的鍺量子點並且有對稱的穿隧介電層。接著使用電子束微影並搭配電極圖案的設計去定義元件之各端電極，簡化了以往製作單電子電晶體時因為源/汲電極與閘電極是分別去定義與形成，會有比較複雜之製程步驟。最後我們利用分析訊號以及蝕刻的方式來去大量降低在兩道微影對準製程時之不確定性，使平均對準偏移量控制得以在15 nm以內。在溫度為120 K至80 K的電性量測下，元件展現出相當清晰並且有可意義的庫倫震盪現象。最後我們分別從結構上以及量測結果上估算單電子電晶體特性參數，並進行比較與分析。Single-electron transistors (SET) offer great potential for high charge sensitivity and low-power consumption. Besides, it’s a rational quantum device which conforms to the historical trend of the device scaling. This thesis has redesigned and reformed the SET device originated from our group before for the purpose to promote the yield rate and advance the electrical performance.In this thesis, we demonstrated the fabrication and electrical characterizations of germanium quantum dot (Ge QD) in planar structure. We are able to position and number Ge QDs by means of fabricating a nano-cavity. After thermal oxidizing the SiGe polygonal in the nano-cavity, it produced a single Ge QD in the center with symmetrical tunneling junction. Instead of quite complicated SET process of the past that made Gate and S/D to be defined respectively, all electrodes are formed together for this SET device by particularity patterning with electronic beam lithography. Additionally, through suitable signal processing to alleviate the uncertainty of lithography alignment, we successfully reduce miss alignment to less than 15 nm in average.The fabricated Ge QD SET exhibits reliable and clear Coulomb oscillation behaviors under gate and drain modulation at T = 80 K－120 K. In addition, we make some preliminary estimates from device structure, and compare them with measurement data.
