微波毫米波寬頻振盪器與鎖相迴路之研製;Microwave and Millimeter-wave Broadband Oscillator and Phase-locked Loop

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題名:	微波毫米波寬頻振盪器與鎖相迴路之研製;Microwave and Millimeter-wave Broadband Oscillator and Phase-locked Loop
作者:	廖彥涵;Liao,Yen-han
貢獻者:	電機工程學系
關鍵詞:	振盪器;正交振盪器;注入鎖定;鎖相迴路;Injection-locked;Phase-lock loop;QVCO;voltage-controlled oscillator
日期:	2013-03-12
上傳時間:	2013-06-19 15:26:34 (UTC+8)
出版者:	國立中央大學
摘要:	??近年來無線通訊產業快速發展，關鍵技術日趨成熟，但是射頻無線積體電路的製作價格仍然偏高，為了降低製作成本及整合數位類比電路於單一晶片上，採用低價格的互補式金屬氧化物半導體製程來開發設計，已是未來的發展趨勢。在無線通訊的收發機中，低相位雜訊的壓控振盪器是不可或缺的元件，如何設計高頻率並同時具有低相位雜訊的振盪器是一個值得探討的主題。鎖相迴路則是穩定壓控振盪器輸出頻率的方法之一，將注入鎖定技術應用於振盪器、除頻器、鎖相迴路與等主動電路，可以改善本地振盪源之電路性能。在通訊系統中，常將訊號分成I/Q兩通道，增加其適用的頻寬，因此收發電路中常需使用四相位正交訊號輸出的振盪器，才可進行調變或解調。本論文內容分成四部分，第二章設計三種應用於K頻段的寬頻差動振盪器，第三章設計注入鎖定倍頻器，第四章提出新型四相位壓控振盪器，第五章提出注入鎖定除六除頻器並應用於K頻段鎖相迴路，並對振幅及相位誤差作分析探討。??第二章為使用穩懋砷化鎵為材質之異質接面雙極性電晶體，和假晶格高速電子移動率電晶體製程，設計三種應用於K頻段的低功耗低相位雜訊的差動壓控振盪器，包括基本的共基極差動振盪器，將異質接面雙極性電晶體疊接假晶格高速電子移動率電晶體的共射極差動振盪器，以及使用主動負載共射極差動振盪器，對電路做負阻及頻寬的分析。三種電路可調頻寬的百分比分別達到38.3%、22%、31.3%，晶片面積均為1×1 mm2，與近年文獻比較均有較佳的頻寬及優化指數的表現。??第三章為注入鎖定倍頻器的設計與分析。由於高頻特性受限於元件，直接實現一高頻壓控振盪器是不容易的，此電路利用較低頻的振盪器串接倍頻器在想要的頻段獲得訊號，並使用台積電提供的0.18 μm矽鍺雙載子互補金氧半導體製程實現。由量測結果得知，可調頻寬範圍17.08至18.37 GHz，其輸出功率均高於－8.4 dBm，輸出頻率為18.4 GHz時，偏移中心頻 1 MHz 量測之輸出相位雜訊為－99.8 dBc/Hz，鎖定頻寬有1.4 GHz，直流功率消耗為7 mW，晶片面積為0.49×0.73 mm2。??第四章介紹四相位壓控振盪器的原理與架構，並提出新型的四相位振盪器，同時說明其設計概念及直接量測相位、振幅誤差的方法。使用台積電90 nm CMOS製程實現了K頻段使用變壓器回授及閘極調變架構之壓控振盪器，振盪頻率可調範圍為1.7 GHz，輸出功率為－9.6 dBm，輸出頻率為25.07 GHz時，偏移中心頻 1 MHz 量測之輸出相位雜訊為－98.6 dBc/Hz，量測到最小的振幅誤差為0.55 dB，相位誤差為0.28°，直流功率消耗為16.15 mW，晶片面積為0.74×0.89 mm2。優位指數為－174.4 dBc/Hz。 ??第五章介紹基本除頻器架構以及設計原理，同時採用台積電提供的0.18 μm 互補式金屬氧化物半導體製程實現一個除五注入鎖定除頻器，量測最大鎖定頻寬為1.1 GHz。將此注入鎖定除頻器整合至鎖相迴路系統，包含注入鎖定壓控振盪器、相位頻率偵測器、電荷幫浦、迴路濾波器及除頻鏈，同樣是使用台積電0.18 μm互補式金屬氧化物半導體製程實現，其鎖定頻率範圍為22.09至22.19 GHz，未注入前，鎖定頻率為22.15 GHz 時，在偏移中心頻 1 MHz 量測之輸出相位雜訊為－104 dBc/Hz，注入後，當鎖定頻率為22.15 GHz 時，在偏移中心頻 1 MHz 量測之輸出相位雜訊為－130 dBc/Hz，迴路中使用注入鎖定振盪器改善了鎖相迴路的相位雜訊，提供品質更好的本地振盪源。此電路總共直流消耗為102 mW，晶片面積為1.06×1.395 mm2。??For a transceiver in wireless communication, the low phase noise local oscillator (LO) source is an indispensable element, since it is an important issue for designing a high-frequency and low phase noise LO source is an important issue. The phase-locked loop (PLL) is one of the methods to stabilize the output frequency of the voltage-controlled oscillator (VCO). In order to provide system with a stable and low phase noise LO source for the microwave and millimeter wave (MMW) system, an injection-locked technique can be adopted to enhance the operation frequency for many active circuits, such as oscillator, frequency divider, PLL, and frequency multiplier. A key building block in the LO source is the VCO with quadrature outputs. The quadrature VCO (QVCO) is needed for I/Q modulation or demodulation.??In Chapter 2, three K-band differential VCOs, including a conventional common-base VCO, a cascode commom-emitter VCO and a conventional commom-emitter VCO with active load, have been designed using WIN Semiconductors 0.5-μm PHEMT and 2-μm HBT technology. The negative resistance of the HBT-HEMT cascode VCO is analyzed. The tuning bandwidth of the differential VCOs are 38.3%、22% and 31.3%. The CB differential VCOs demonstrates the widest bandwidth among the relevant literatures.??The design and analysis of an injection-locked oscillator (ILO) is presented in Chapter 3. Simulated normalized third harmonic currents of the frequency pre-generator as a function of base current, and select the base current for higher frequency conversion ef?ciency while maintaining oscillation. The ILO with a locking range of 1.4 GHz is realized using TSMC 0.18-μm SiGe BiCMOS process. The measured maximum output frequency is 18.37 GHz.??In the Chapter 4, we used TSMC 90-nm CMOS process to realize a K-band VCO with transformer-feedback and gate-modulation techniques. The analysis for generating quadrature is presented in detailed manner.The measured oscillation frequency is from 23.4 to 25.1 GHz. The measured phase noise is －98.6 dBc/Hz at 1-MHz offset. The dc power consumption is 16.15 mW and the RF output power is －9.6 dBm. The minimum I/Q phase and amplitude error are 0.28° and 0.55 dB, respectively. The VCO demonstrates a figure of merit (FOM) of －174.4 dBc/Hz. ??The analysis and design of the ILFD are presented in Chapter 5. The divide-by-6 ILFD with a locking range of 1.1 GHz is fabricated using TSMC 0.18-μm CMOS process. Moreover, the proposed ILFD is applied to a fully integrated PLL, and the measured frequency of the PLL is from 22.09 to 22.19 GHz. The measured phase noise with injection signal is ?130 dBc/Hz at 1 MHz offset. The dc power consumption is 102 mW. The inection-locked technique is used to improve the phase noise of the PLL. The conclusion is given in Chapter 6.
顯示於類別:	[電機工程研究所] 博碩士論文

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