本論文主要包含兩主題，第一部份為使用fT-倍頻電路設計毫米波壓控振盪器，首先將對於壓控振盪器和相位雜訊生成做介紹與描述，最後實現兩個V頻段壓控振盪器。第二部份使用fT-倍頻電路設計注入鎖定除頻器，分別對於除頻器架構作簡介，最後實現一個K頻段注入鎖定除頻器。以上電路分別使用tsmcTM 0.18-μm CMOS和tsmcTM 90-nm CMOS製程實現設計。 第一部份設計二個毫米波壓控振盪器，同時以fT-倍頻電路架構作為設計核心，第一個振盪器為應用於V頻段之新型fT-倍頻架構壓控振盪器，使用tsmcTM 90 nm CMOS製程，量測結果顯示，操作電壓1.2 V下，功率消耗約為2.076 mW，操作頻率約為58.52 GHz，可調頻率範圍為58.52 到 59.62 GHz，相位雜訊在偏移1 MHz時為 -92.098 dBc/Hz，證實此新型fT-倍頻壓控振盪器電路架構具有低相位雜訊及低功率消耗之特性，最大輸出功率約為 -15.41 dBm，優化指數為 -184.27 dBc/Hz，晶片面積為0.417 mm^2。另外一個振盪器為V頻段之fT-倍頻架構使用振幅分佈式壓控振盪器，將討論尾電流源所貢獻的閃爍雜訊，及探討電晶體的偏壓方式，讓壓控振盪器的相位雜訊有最佳化的表現。使用tsmcTM 90 nm CMOS製程，量測結果為，於操作電壓為1.2 V下，功率消耗約為10.9 mW，操作頻率約為60.72 GHz，可調範圍為59.58 到 60.72 GHz，相位雜訊在偏移1 MHz時為 -90.46 dBc/Hz，最大輸出功率約為 -8.3 dBm，優化指數為 -175.75 dBc/Hz，晶片面積為0.626 mm^2。 第二部份為設計一個注入鎖定除頻器，同樣以fT-倍頻電路架構作為核心，設計應用於K頻段之新型fT-倍頻架構注入鎖定除頻器，使用tsmcTM 0.18 μm CMOS製程，實現低功耗之K頻段除二除頻器，在輸入功率於0 dBm 下，鎖定頻率範圍為20.5~22.9 GHz，達11.06 %的鎖定範圍，功率消耗為1.728 mW ，其優化指數為 6.4 %/mW^2，晶片面積為0.594 mm^2。 最後將於最後一章，討論以上三顆晶片優劣處，並設定自己對於未來的期許和努力方向。 The thesis studies two subjects. The first one is on millimeter-wave voltage controlled oscillator (VCO) design where two V-band VCOs are demonstrated. The second one is on injection locked frequency divider (ILFD) design where a K-band ILFD is demonstrated. The circuits were implemented in tsmcTM 90-nm CMOS and tsmcTM 0.18-μm CMOS technologies. The first part of this thesis presents two millimeter-wave VCOs using the fT-doubler cell. The proposed novel V-band fT-doubler VCO is implemented in tsmcTM 90-nm CMOS technology, which performs low power dissipation and low phase noise. The oscillation frequency is 58.52 GHz with the tuning range of 1100 MHz under a supply voltage of 1.2 V. The power consumption is 2.076 mW. The measured phase noise is -92.098 dBc/Hz at 1-MHz offset frequency. The calculated figure of merit (FOM) is -184.27 dBc/Hz. The chip size is 0.417 mm^2. The second circuit is a V-band fT-doubler VCO adopting bias level shifting technique which solves the flicker noise contributed from current source. The DC bias voltage of transistors is discussed, and then the phase noise is optimized. This VCO circuit was implemented in tsmcTM 90-nm CMOS technology. The operating frequency is 60.72 GHz with the tuning range of 1140 MHz under a supply voltage of 1.2 V. The power consumption is 10.9 mW. The measured phase noise is -90.46 dBc/Hz at 1-MHz offset frequency. The calculated FOM is -175.75 dBc/Hz. The chip size is 0.626 mm^2. The second part of this thesis developed ILFD design using the fT-doubler cell. A novel fT-doubler technique is applied to a K-band ILFD design, this technique provides a wide locking range under low power dissipation. This K-band ILFD is implemented in tsmcTM 0.18-μm CMOS process. The obtained locking range is 20.5 to 22.9 GHz (11.06 %) at 0-dBm input power and 1.2-V supply voltage. The power consumption is 1.728 mW. The FOM is 6.4 %/mW^2. The chip size is 0.594 mm^2. Finally, a brief conclusion is given in Chapter 5.
