應用於生理訊號偵測之截波穩定型類比前端電路之設計;A Design of Analog Front-End Circuit Based on Chopper Stabilization Technique for Bio-Signal Detection

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題名:	應用於生理訊號偵測之截波穩定型類比前端電路之設計;A Design of Analog Front-End Circuit Based on Chopper Stabilization Technique for Bio-Signal Detection
作者:	林哲生;Lin,Jer-sheng
貢獻者:	電機工程學系
關鍵詞:	生醫晶片;類比前端電路;截波穩定技術;integrated circuit of bio-medical signal;analog front end circuit;chopper stabilization technique
日期:	2014-07-21
上傳時間:	2014-10-15 17:09:08 (UTC+8)
出版者:	國立中央大學
摘要:	近幾年來隨著科技的進步、無線傳輸技術的成熟與網際網路的普及性，生醫感測技術結合無線網路在未來的醫療系統發展上將會受到重視，尤其是個人居家以及普通病房環境中的監控需求，因此，考量到便利性，我們希望病人可以攜帶輕巧的監控裝置並長時間的監控生理狀況。由於電極端接收的生理訊號極為微弱，為了完整地記錄生理訊號，其電路設計上朝向低雜訊、高解析度、低功率消耗等特點邁進。本篇主旨為應用於生理訊號偵測系統之全差動對稱式類比前端電路設計，是針對微弱的心電(Electrocardiography, ECG)訊號作記錄。為了將低頻雜訊的成份濾除，本電路的放大級採用截波穩定技術作為降低雜訊的方法；再來，為了消除輸入半細胞電位的影響，我們在系統第一級的部分加入高通濾波器；以上所使用兩個方法最後，其目的都是為了提高訊號的解析度；最後，為了降低整體電路的功率消耗，所以將放大器的輸入級的場效電晶體操作於弱反轉區，目的是為了利用小電流以得到大的轉導值。以上說明了我們是如何達到低雜訊、高解析度、低功率等特點的。本文所提出的類比前端電路系統包含高通濾波器、截波穩定型帶通濾波器、二階低通濾波器、偏壓電路與時脈產生器。在電路實現上，在有效頻寬約1.5KHz 下、直流增益為40dB、總等效輸入相關雜訊電壓約為12.61μVrms、其有效位元數達到11位元的解析度。使用台積電0.18 μm 標準CMOS 1P6M 製程完成，其晶片面積為1.17048 × 898 mm2。在1.8 V 電源供應下，總功率消耗約為6.23 μW。 ;Because of the advanced technique and the development of health awareness in recent years, the combination of the biomedical sensing technique and wireless network become more popular, especially for elder care and video games. To make the products more convenient for users, one of our goals is to make the product portable, and the other is to prolong the battery Life. Due to the biomedical signals are very sensitive to the noise and the offset, the design of cancelling non-ideal low frequency effects is indispensable. In this thesis, we present a fully differential analog front- end circuit for bio-signal detection system that can be used to record the electrocadiography, ECG, signal. To make the output signal offer a higher resolution, we employ the high pass filter in the first stage to eliminate the half-cell voltage, and chopper stabilization technique is employed in the amplification stage to eliminate the non-ideal low frequency effects, such as flicker noise and DC offset voltage. In order to decrease the power dissipation of the system, the input stages of the amplifier are designed to operate in weak inversion region. The analog front-end system designed includes a high pass filter, a chopper stabilization amplifier, a second order low pass filter, a bias circuit and a clock generator. Our AFE circuit design achieves 130dB CMRR, 1.89-μV_rms input refer noise in the range of 0.1 to 150 Hz and 11bits resolution, while consuming 11.56μW. And the AFE system is implemented by TSMC with 0.18-μm 1P6M CMOS process. The superficial measure of the chip is 1.17048×0.898 〖mm〗^2.
顯示於類別:	[電機工程研究所] 博碩士論文

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